include/linux/soc/mediatek/infracfg.h

Source file repositories/reference/linux-study-clean/include/linux/soc/mediatek/infracfg.h

File Facts

System
Linux kernel
Corpus path
include/linux/soc/mediatek/infracfg.h
Extension
.h
Size
22134 bytes
Lines
458
Domain
Core OS
Bucket
Core Kernel Interface
Inferred role
Core OS: implementation source
Status
source implementation candidate

Why This File Exists

Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SOC_MEDIATEK_INFRACFG_H
#define __SOC_MEDIATEK_INFRACFG_H

#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1				0x228
#define MT8365_INFRA_TOPAXI_PROTECTEN_SET				0x2a0
#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR				0x2a4
#define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0				BIT(1)
#define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1				BIT(2)
#define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S				BIT(6)
#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0		BIT(10)
#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1		BIT(11)
#define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB			BIT(13)
#define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB			BIT(14)
#define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0				BIT(21)
#define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG			BIT(22)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1				0x258
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET				0x2a8
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR				0x2ac
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP				BIT(2)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0	BIT(16)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1	BIT(17)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST	BIT(18)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST		BIT(19)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST		BIT(20)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV	BIT(21)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB	BIT(24)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO		BIT(27)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M		BIT(28)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M		BIT(30)
#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S		BIT(31)

#define MT8365_INFRA_NAO_TOPAXI_SI0_STA					0x0
#define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED			BIT(24)
#define MT8365_INFRA_NAO_TOPAXI_SI2_STA					0x28
#define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED			BIT(14)
#define MT8365_INFRA_TOPAXI_SI0_CTL					0x200
#define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S				BIT(6)
#define MT8365_INFRA_TOPAXI_SI2_CTL					0x234
#define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1				BIT(5)

#define MT8365_SMI_COMMON_CLAMP_EN			0x3c0
#define MT8365_SMI_COMMON_CLAMP_EN_SET			0x3c4
#define MT8365_SMI_COMMON_CLAMP_EN_CLR			0x3c8

#define MT8195_TOP_AXI_PROT_EN_STA1                     0x228
#define MT8195_TOP_AXI_PROT_EN_1_STA1                   0x258
#define MT8195_TOP_AXI_PROT_EN_SET			0x2a0
#define MT8195_TOP_AXI_PROT_EN_CLR                      0x2a4
#define MT8195_TOP_AXI_PROT_EN_1_SET                    0x2a8
#define MT8195_TOP_AXI_PROT_EN_1_CLR                    0x2ac
#define MT8195_TOP_AXI_PROT_EN_MM_SET                   0x2d4
#define MT8195_TOP_AXI_PROT_EN_MM_CLR                   0x2d8
#define MT8195_TOP_AXI_PROT_EN_MM_STA1                  0x2ec
#define MT8195_TOP_AXI_PROT_EN_2_SET                    0x714
#define MT8195_TOP_AXI_PROT_EN_2_CLR                    0x718
#define MT8195_TOP_AXI_PROT_EN_2_STA1                   0x724
#define MT8195_TOP_AXI_PROT_EN_VDNR_SET                 0xb84
#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR                 0xb88
#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1                0xb90
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET               0xba4
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR               0xba8
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1              0xbb0
#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET               0xbb8
#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR               0xbbc
#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1              0xbc4
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET       0xbcc
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR       0xbd0
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1      0xbd8
#define MT8195_TOP_AXI_PROT_EN_MM_2_SET                 0xdcc
#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR                 0xdd0
#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1                0xdd8

#define MT8195_TOP_AXI_PROT_EN_VDOSYS0			BIT(6)
#define MT8195_TOP_AXI_PROT_EN_VPPSYS0			BIT(10)
#define MT8195_TOP_AXI_PROT_EN_MFG1			BIT(11)
#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND			GENMASK(22, 21)
#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND		BIT(23)
#define MT8195_TOP_AXI_PROT_EN_1_MFG1			GENMASK(20, 19)
#define MT8195_TOP_AXI_PROT_EN_1_CAM			BIT(22)
#define MT8195_TOP_AXI_PROT_EN_2_CAM			BIT(0)
#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND		GENMASK(6, 5)
#define MT8195_TOP_AXI_PROT_EN_2_MFG1			BIT(7)
#define MT8195_TOP_AXI_PROT_EN_2_AUDIO			(BIT(9) | BIT(11))
#define MT8195_TOP_AXI_PROT_EN_2_ADSP			(BIT(12) | GENMASK(16, 14))
#define MT8195_TOP_AXI_PROT_EN_MM_CAM			(BIT(0) | BIT(2) | BIT(4))
#define MT8195_TOP_AXI_PROT_EN_MM_IPE			BIT(1)
#define MT8195_TOP_AXI_PROT_EN_MM_IMG			BIT(3)
#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0		GENMASK(21, 17)
#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1		GENMASK(8, 5)
#define MT8195_TOP_AXI_PROT_EN_MM_VENC			(BIT(9) | BIT(11))

Annotation

Implementation Notes