include/linux/soundwire/sdw_registers.h

Source file repositories/reference/linux-study-clean/include/linux/soundwire/sdw_registers.h

File Facts

System
Linux kernel
Corpus path
include/linux/soundwire/sdw_registers.h
Extension
.h
Size
12356 bytes
Lines
361
Domain
Core OS
Bucket
Core Kernel Interface
Inferred role
Core OS: implementation source
Status
source implementation candidate

Why This File Exists

Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SDW_REGISTERS_H
#define __SDW_REGISTERS_H

#include <linux/bitfield.h>
#include <linux/bits.h>

/*
 * SDW registers as defined by MIPI 1.2 Spec
 */
#define SDW_REGADDR				GENMASK(14, 0)
#define SDW_SCP_ADDRPAGE2_MASK			GENMASK(22, 15)
#define SDW_SCP_ADDRPAGE1_MASK			GENMASK(30, 23)

#define SDW_REG_NO_PAGE				0x00008000
#define SDW_REG_OPTIONAL_PAGE			0x00010000
#define SDW_REG_MAX				0x48000000

#define SDW_DPN_SIZE				0x100
#define SDW_BANK1_OFFSET			0x10

/*
 * DP0 Interrupt register & bits
 *
 * Spec treats Status (RO) and Clear (WC) as separate but they are same
 * address, so treat as same register with WC.
 */

/* both INT and STATUS register are same */
#define SDW_DP0_INT				0x0
#define SDW_DP0_INTMASK				0x1
#define SDW_DP0_PORTCTRL			0x2
#define SDW_DP0_BLOCKCTRL1			0x3
#define SDW_DP0_PREPARESTATUS			0x4
#define SDW_DP0_PREPARECTRL			0x5

#define SDW_DP0_INT_TEST_FAIL			BIT(0)
#define SDW_DP0_INT_PORT_READY			BIT(1)
#define SDW_DP0_INT_BRA_FAILURE			BIT(2)
#define SDW_DP0_SDCA_CASCADE			BIT(3)
/* BIT(4) not allocated in SoundWire specification 1.2 */
#define SDW_DP0_INT_IMPDEF1			BIT(5)
#define SDW_DP0_INT_IMPDEF2			BIT(6)
#define SDW_DP0_INT_IMPDEF3			BIT(7)
#define SDW_DP0_INTERRUPTS			(SDW_DP0_INT_TEST_FAIL | \
						 SDW_DP0_INT_PORT_READY | \
						 SDW_DP0_INT_BRA_FAILURE | \
						 SDW_DP0_INT_IMPDEF1 | \
						 SDW_DP0_INT_IMPDEF2 | \
						 SDW_DP0_INT_IMPDEF3)

#define SDW_DP0_PORTCTRL_DATAMODE		GENMASK(3, 2)
#define SDW_DP0_PORTCTRL_NXTINVBANK		BIT(4)
#define SDW_DP0_PORTCTRL_BPT_PAYLD		GENMASK(7, 6)

#define SDW_DP0_CHANNELEN			0x20
#define SDW_DP0_SAMPLECTRL1			0x22
#define SDW_DP0_SAMPLECTRL2			0x23
#define SDW_DP0_OFFSETCTRL1			0x24
#define SDW_DP0_OFFSETCTRL2			0x25
#define SDW_DP0_HCTRL				0x26
#define SDW_DP0_LANECTRL			0x28

/* Both INT and STATUS register are same */
#define SDW_SCP_INT1				0x40
#define SDW_SCP_INTMASK1			0x41

#define SDW_SCP_INT1_PARITY			BIT(0)
#define SDW_SCP_INT1_BUS_CLASH			BIT(1)
#define SDW_SCP_INT1_IMPL_DEF			BIT(2)
#define SDW_SCP_INT1_SCP2_CASCADE		BIT(7)
#define SDW_SCP_INT1_PORT0_3			GENMASK(6, 3)

#define SDW_SCP_INTSTAT2			0x42
#define SDW_SCP_INTSTAT2_SCP3_CASCADE		BIT(7)
#define SDW_SCP_INTSTAT2_PORT4_10		GENMASK(6, 0)

#define SDW_SCP_INTSTAT3			0x43
#define SDW_SCP_INTSTAT3_PORT11_14		GENMASK(3, 0)

/* Number of interrupt status registers */
#define SDW_NUM_INT_STAT_REGISTERS		3

/* Number of interrupt clear registers */
#define SDW_NUM_INT_CLEAR_REGISTERS		1

#define SDW_SCP_CTRL				0x44
#define SDW_SCP_CTRL_CLK_STP_NOW		BIT(1)
#define SDW_SCP_CTRL_FORCE_RESET		BIT(7)

#define SDW_SCP_STAT				0x44

Annotation

Implementation Notes