include/soc/fsl/qe/immap_qe.h

Source file repositories/reference/linux-study-clean/include/soc/fsl/qe/immap_qe.h

File Facts

System
Linux kernel
Corpus path
include/soc/fsl/qe/immap_qe.h
Extension
.h
Size
15446 bytes
Lines
467
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

struct qe_iram {
	__be32	iadd;		/* I-RAM Address Register */
	__be32	idata;		/* I-RAM Data Register */
	u8	res0[0x04];
	__be32	iready;		/* I-RAM Ready Register */
	u8	res1[0x70];
} __attribute__ ((packed));

/* QE Interrupt Controller */
struct qe_ic_regs {
	__be32	qicr;
	__be32	qivec;
	__be32	qripnr;
	__be32	qipnr;
	__be32	qipxcc;
	__be32	qipycc;
	__be32	qipwcc;
	__be32	qipzcc;
	__be32	qimr;
	__be32	qrimr;
	__be32	qicnr;
	u8	res0[0x4];
	__be32	qiprta;
	__be32	qiprtb;
	u8	res1[0x4];
	__be32	qricr;
	u8	res2[0x20];
	__be32	qhivec;
	u8	res3[0x1C];
} __attribute__ ((packed));

/* Communications Processor */
struct cp_qe {
	__be32	cecr;		/* QE command register */
	__be32	ceccr;		/* QE controller configuration register */
	__be32	cecdr;		/* QE command data register */
	u8	res0[0xA];
	__be16	ceter;		/* QE timer event register */
	u8	res1[0x2];
	__be16	cetmr;		/* QE timers mask register */
	__be32	cetscr;		/* QE time-stamp timer control register */
	__be32	cetsr1;		/* QE time-stamp register 1 */
	__be32	cetsr2;		/* QE time-stamp register 2 */
	u8	res2[0x8];
	__be32	cevter;		/* QE virtual tasks event register */
	__be32	cevtmr;		/* QE virtual tasks mask register */
	__be16	cercr;		/* QE RAM control register */
	u8	res3[0x2];
	u8	res4[0x24];
	__be16	ceexe1;		/* QE external request 1 event register */
	u8	res5[0x2];
	__be16	ceexm1;		/* QE external request 1 mask register */
	u8	res6[0x2];
	__be16	ceexe2;		/* QE external request 2 event register */
	u8	res7[0x2];
	__be16	ceexm2;		/* QE external request 2 mask register */
	u8	res8[0x2];
	__be16	ceexe3;		/* QE external request 3 event register */
	u8	res9[0x2];
	__be16	ceexm3;		/* QE external request 3 mask register */
	u8	res10[0x2];
	__be16	ceexe4;		/* QE external request 4 event register */
	u8	res11[0x2];
	__be16	ceexm4;		/* QE external request 4 mask register */
	u8	res12[0x3A];
	__be32	ceurnr;		/* QE microcode revision number register */
	u8	res13[0x244];
} __attribute__ ((packed));

/* QE Multiplexer */
struct qe_mux {
	__be32	cmxgcr;		/* CMX general clock route register */
	__be32	cmxsi1cr_l;	/* CMX SI1 clock route low register */
	__be32	cmxsi1cr_h;	/* CMX SI1 clock route high register */
	__be32	cmxsi1syr;	/* CMX SI1 SYNC route register */
	__be32	cmxucr[4];	/* CMX UCCx clock route registers */
	__be32	cmxupcr;	/* CMX UPC clock route register */
	u8	res0[0x1C];
} __attribute__ ((packed));

/* QE Timers */
struct qe_timers {
	u8	gtcfr1;		/* Timer 1 and Timer 2 global config register*/
	u8	res0[0x3];
	u8	gtcfr2;		/* Timer 3 and timer 4 global config register*/
	u8	res1[0xB];
	__be16	gtmdr1;		/* Timer 1 mode register */
	__be16	gtmdr2;		/* Timer 2 mode register */
	__be16	gtrfr1;		/* Timer 1 reference register */
	__be16	gtrfr2;		/* Timer 2 reference register */

Annotation

Implementation Notes