include/soc/spacemit/k3-syscon.h

Source file repositories/reference/linux-study-clean/include/soc/spacemit/k3-syscon.h

File Facts

System
Linux kernel
Corpus path
include/soc/spacemit/k3-syscon.h
Extension
.h
Size
8657 bytes
Lines
274
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SOC_K3_SYSCON_H__
#define __SOC_K3_SYSCON_H__

#include "ccu.h"

/* APBS register offset */
#define APBS_PLL1_SWCR1			0x100
#define APBS_PLL1_SWCR2			0x104
#define APBS_PLL1_SWCR3			0x108
#define APBS_PLL2_SWCR1			0x118
#define APBS_PLL2_SWCR2			0x11c
#define APBS_PLL2_SWCR3			0x120
#define APBS_PLL3_SWCR1			0x124
#define APBS_PLL3_SWCR2			0x128
#define APBS_PLL3_SWCR3			0x12c
#define APBS_PLL4_SWCR1			0x130
#define APBS_PLL4_SWCR2			0x134
#define APBS_PLL4_SWCR3			0x138
#define APBS_PLL5_SWCR1			0x13c
#define APBS_PLL5_SWCR2			0x140
#define APBS_PLL5_SWCR3			0x144
#define APBS_PLL6_SWCR1			0x148
#define APBS_PLL6_SWCR2			0x14c
#define APBS_PLL6_SWCR3			0x150
#define APBS_PLL7_SWCR1			0x158
#define APBS_PLL7_SWCR2			0x15c
#define APBS_PLL7_SWCR3			0x160
#define APBS_PLL8_SWCR1			0x180
#define APBS_PLL8_SWCR2			0x184
#define APBS_PLL8_SWCR3			0x188

/* MPMU register offset */
#define MPMU_FCCR			0x0008
#define MPMU_POSR			0x0010
#define POSR_PLL1_LOCK			BIT(24)
#define POSR_PLL2_LOCK			BIT(25)
#define POSR_PLL3_LOCK			BIT(26)
#define POSR_PLL4_LOCK			BIT(27)
#define POSR_PLL5_LOCK			BIT(28)
#define POSR_PLL6_LOCK			BIT(29)
#define POSR_PLL7_LOCK			BIT(30)
#define POSR_PLL8_LOCK			BIT(31)
#define MPMU_SUCCR			0x0014
#define MPMU_ISCCR			0x0044
#define MPMU_WDTPCR			0x0200
#define MPMU_RIPCCR			0x0210
#define MPMU_ACGR			0x1024
#define MPMU_APBCSCR			0x1050
#define MPMU_SUCCR_1			0x10b0

#define MPMU_I2S0_SYSCLK		0x1100
#define MPMU_I2S2_SYSCLK		0x1104
#define MPMU_I2S3_SYSCLK		0x1108
#define MPMU_I2S4_SYSCLK		0x110c
#define MPMU_I2S5_SYSCLK		0x1110
#define MPMU_I2S_SYSCLK_CTRL		0x1114

/* APBC register offset */
#define APBC_UART0_CLK_RST		0x00
#define APBC_UART2_CLK_RST		0x04
#define APBC_GPIO_CLK_RST		0x08
#define APBC_PWM0_CLK_RST		0x0c
#define APBC_PWM1_CLK_RST		0x10
#define APBC_PWM2_CLK_RST		0x14
#define APBC_PWM3_CLK_RST		0x18
#define APBC_TWSI8_CLK_RST		0x20
#define APBC_UART3_CLK_RST		0x24
#define APBC_RTC_CLK_RST		0x28
#define APBC_TWSI0_CLK_RST		0x2c
#define APBC_TWSI1_CLK_RST		0x30
#define APBC_TIMERS0_CLK_RST		0x34
#define APBC_TWSI2_CLK_RST		0x38
#define APBC_AIB_CLK_RST		0x3c
#define APBC_TWSI4_CLK_RST		0x40
#define APBC_TIMERS1_CLK_RST		0x44
#define APBC_ONEWIRE_CLK_RST		0x48
#define APBC_TWSI5_CLK_RST		0x4c
#define APBC_DRO_CLK_RST		0x58
#define APBC_IR0_CLK_RST		0x5c
#define APBC_IR1_CLK_RST		0x1c
#define APBC_TWSI6_CLK_RST		0x60
#define APBC_COUNTER_CLK_SEL		0x64
#define APBC_TSEN_CLK_RST		0x6c
#define APBC_UART4_CLK_RST		0x70
#define APBC_UART5_CLK_RST		0x74
#define APBC_UART6_CLK_RST		0x78
#define APBC_SSP3_CLK_RST		0x7c
#define APBC_SSPA0_CLK_RST		0x80
#define APBC_SSPA1_CLK_RST		0x84
#define APBC_SSPA2_CLK_RST		0x88

Annotation

Implementation Notes