include/uapi/drm/i915_drm.h

Source file repositories/reference/linux-study-clean/include/uapi/drm/i915_drm.h

File Facts

System
Linux kernel
Corpus path
include/uapi/drm/i915_drm.h
Extension
.h
Size
131782 bytes
Lines
3917
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

struct i915_user_extension {
	/**
	 * @next_extension:
	 *
	 * Pointer to the next struct i915_user_extension, or zero if the end.
	 */
	__u64 next_extension;
	/**
	 * @name: Name of the extension.
	 *
	 * Note that the name here is just some integer.
	 *
	 * Also note that the name space for this is not global for the whole
	 * driver, but rather its scope/meaning is limited to the specific piece
	 * of uAPI which has embedded the struct i915_user_extension.
	 */
	__u32 name;
	/**
	 * @flags: MBZ
	 *
	 * All undefined bits must be zero.
	 */
	__u32 flags;
	/**
	 * @rsvd: MBZ
	 *
	 * Reserved for future use; must be zero.
	 */
	__u32 rsvd[4];
};

/*
 * MOCS indexes used for GPU surfaces, defining the cacheability of the
 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
 */
enum i915_mocs_table_index {
	/*
	 * Not cached anywhere, coherency between CPU and GPU accesses is
	 * guaranteed.
	 */
	I915_MOCS_UNCACHED,
	/*
	 * Cacheability and coherency controlled by the kernel automatically
	 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
	 * usage of the surface (used for display scanout or not).
	 */
	I915_MOCS_PTE,
	/*
	 * Cached in all GPU caches available on the platform.
	 * Coherency between CPU and GPU accesses to the surface is not
	 * guaranteed without extra synchronization.
	 */
	I915_MOCS_CACHED,
};

/**
 * enum drm_i915_gem_engine_class - uapi engine type enumeration
 *
 * Different engines serve different roles, and there may be more than one
 * engine serving each role.  This enum provides a classification of the role
 * of the engine, which may be used when requesting operations to be performed
 * on a certain subset of engines, or for providing information about that
 * group.
 */
enum drm_i915_gem_engine_class {
	/**
	 * @I915_ENGINE_CLASS_RENDER:
	 *
	 * Render engines support instructions used for 3D, Compute (GPGPU),
	 * and programmable media workloads.  These instructions fetch data and
	 * dispatch individual work items to threads that operate in parallel.
	 * The threads run small programs (called "kernels" or "shaders") on
	 * the GPU's execution units (EUs).
	 */
	I915_ENGINE_CLASS_RENDER	= 0,

	/**
	 * @I915_ENGINE_CLASS_COPY:
	 *
	 * Copy engines (also referred to as "blitters") support instructions
	 * that move blocks of data from one location in memory to another,
	 * or that fill a specified location of memory with fixed data.
	 * Copy engines can perform pre-defined logical or bitwise operations
	 * on the source, destination, or pattern data.
	 */
	I915_ENGINE_CLASS_COPY		= 1,

	/**
	 * @I915_ENGINE_CLASS_VIDEO:
	 *

Annotation

Implementation Notes