include/uapi/linux/dpll.h
Source file repositories/reference/linux-study-clean/include/uapi/linux/dpll.h
File Facts
- System
- Linux kernel
- Corpus path
include/uapi/linux/dpll.h- Extension
.h- Size
- 9833 bytes
- Lines
- 311
- Domain
- Core OS
- Bucket
- Core Kernel Interface
- Inferred role
- Core OS: implementation source
- Status
- source implementation candidate
Why This File Exists
Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
enum dpll_modeenum dpll_lock_statusenum dpll_lock_status_errorenum dpll_clock_quality_levelenum dpll_typeenum dpll_pin_typeenum dpll_pin_directionenum dpll_pin_stateenum dpll_pin_operstateenum dpll_pin_capabilitiesenum dpll_feature_stateenum dpll_aenum dpll_a_pinenum dpll_cmd
Annotated Snippet
#ifndef _UAPI_LINUX_DPLL_H
#define _UAPI_LINUX_DPLL_H
#define DPLL_FAMILY_NAME "dpll"
#define DPLL_FAMILY_VERSION 1
/**
* enum dpll_mode - working modes a dpll can support, differentiates if and how
* dpll selects one of its inputs to syntonize with it, valid values for
* DPLL_A_MODE attribute
* @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll
* @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll
*/
enum dpll_mode {
DPLL_MODE_MANUAL = 1,
DPLL_MODE_AUTOMATIC,
/* private: */
__DPLL_MODE_MAX,
DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
};
/**
* enum dpll_lock_status - provides information of dpll device lock status,
* valid values for DPLL_A_LOCK_STATUS attribute
* @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or
* forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED)
* @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover
* available
* @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired
* @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or
* was forced by disconnecting all the pins (latter possible only when dpll
* lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state
* was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain
* DPLL_LOCK_STATUS_UNLOCKED)
*/
enum dpll_lock_status {
DPLL_LOCK_STATUS_UNLOCKED = 1,
DPLL_LOCK_STATUS_LOCKED,
DPLL_LOCK_STATUS_LOCKED_HO_ACQ,
DPLL_LOCK_STATUS_HOLDOVER,
/* private: */
__DPLL_LOCK_STATUS_MAX,
DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1)
};
/**
* enum dpll_lock_status_error - if previous status change was done due to a
* failure, this provides information of dpll device lock status error. Valid
* values for DPLL_A_LOCK_STATUS_ERROR attribute
* @DPLL_LOCK_STATUS_ERROR_NONE: dpll device lock status was changed without
* any error
* @DPLL_LOCK_STATUS_ERROR_UNDEFINED: dpll device lock status was changed due
* to undefined error. Driver fills this value up in case it is not able to
* obtain suitable exact error type.
* @DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN: dpll device lock status was changed
* because of associated media got down. This may happen for example if dpll
* device was previously locked on an input pin of type
* PIN_TYPE_SYNCE_ETH_PORT.
* @DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH: the FFO
* (Fractional Frequency Offset) between the RX and TX symbol rate on the
* media got too high. This may happen for example if dpll device was
* previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
*/
enum dpll_lock_status_error {
DPLL_LOCK_STATUS_ERROR_NONE = 1,
DPLL_LOCK_STATUS_ERROR_UNDEFINED,
DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN,
DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH,
/* private: */
__DPLL_LOCK_STATUS_ERROR_MAX,
DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1)
};
/*
* level of quality of a clock device. This mainly applies when the dpll
* lock-status is DPLL_LOCK_STATUS_HOLDOVER. The current list is defined
* according to the table 11-7 contained in ITU-T G.8264/Y.1364 document. One
* may extend this list freely by other ITU-T defined clock qualities, or
* different ones defined by another standardization body (for those, please
* use different prefix).
*/
enum dpll_clock_quality_level {
DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRC = 1,
DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_A,
DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_B,
DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEC1,
DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRTC,
Annotation
- Detected declarations: `enum dpll_mode`, `enum dpll_lock_status`, `enum dpll_lock_status_error`, `enum dpll_clock_quality_level`, `enum dpll_type`, `enum dpll_pin_type`, `enum dpll_pin_direction`, `enum dpll_pin_state`, `enum dpll_pin_operstate`, `enum dpll_pin_capabilities`.
- Atlas domain: Core OS / Core Kernel Interface.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.