include/uapi/linux/virtio_spi.h

Source file repositories/reference/linux-study-clean/include/uapi/linux/virtio_spi.h

File Facts

System
Linux kernel
Corpus path
include/uapi/linux/virtio_spi.h
Extension
.h
Size
7597 bytes
Lines
182
Domain
Core OS
Bucket
Core Kernel Interface
Inferred role
Core OS: implementation source
Status
source implementation candidate

Why This File Exists

Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.

Dependency Surface

Detected Declarations

Annotated Snippet

struct virtio_spi_config {
	__u8 cs_max_number;
	__u8 cs_change_supported;
#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL		_BITUL(0)
#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD		_BITUL(1)
#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL		_BITUL(2)
	__u8 tx_nbits_supported;
	__u8 rx_nbits_supported;
	__le32 bits_per_word_mask;
#define VIRTIO_SPI_MF_SUPPORT_CPHA_0		_BITUL(0)
#define VIRTIO_SPI_MF_SUPPORT_CPHA_1		_BITUL(1)
#define VIRTIO_SPI_MF_SUPPORT_CPOL_0		_BITUL(2)
#define VIRTIO_SPI_MF_SUPPORT_CPOL_1		_BITUL(3)
#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH		_BITUL(4)
#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST		_BITUL(5)
#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK		_BITUL(6)
	__le32 mode_func_supported;
	__le32 max_freq_hz;
	__le32 max_word_delay_ns;
	__le32 max_cs_setup_ns;
	__le32 max_cs_hold_ns;
	__le32 max_cs_inactive_ns;
};

/**
 * struct spi_transfer_head - virtio SPI transfer descriptor
 * @chip_select_id: chipselect index the SPI transfer used.
 * @bits_per_word: the number of bits in each SPI transfer word.
 * @cs_change: whether to deselect device after finishing this transfer
 *     before starting the next transfer, 0 means cs keep asserted and
 *     1 means cs deasserted then asserted again.
 * @tx_nbits: bus width for write transfer.
 *     0,1: bus width is 1, also known as SINGLE
 *     2  : bus width is 2, also known as DUAL
 *     4  : bus width is 4, also known as QUAD
 *     8  : bus width is 8, also known as OCTAL
 *     other values are invalid.
 * @rx_nbits: bus width for read transfer.
 *     0,1: bus width is 1, also known as SINGLE
 *     2  : bus width is 2, also known as DUAL
 *     4  : bus width is 4, also known as QUAD
 *     8  : bus width is 8, also known as OCTAL
 *     other values are invalid.
 * @reserved: for future use.
 * @mode: SPI transfer mode.
 *     bit 0: CPHA, determines the timing (i.e. phase) of the data
 *         bits relative to the clock pulses.For CPHA=0, the
 *         "out" side changes the data on the trailing edge of the
 *         preceding clock cycle, while the "in" side captures the data
 *         on (or shortly after) the leading edge of the clock cycle.
 *         For CPHA=1, the "out" side changes the data on the leading
 *         edge of the current clock cycle, while the "in" side
 *         captures the data on (or shortly after) the trailing edge of
 *         the clock cycle.
 *     bit 1: CPOL, determines the polarity of the clock. CPOL=0 is a
 *         clock which idles at 0, and each cycle consists of a pulse
 *         of 1. CPOL=1 is a clock which idles at 1, and each cycle
 *         consists of a pulse of 0.
 *     bit 2: CS_HIGH, if 1, chip select active high, else active low.
 *     bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB
 *         first, else LSB first.
 *     bit 4: LOOP, loopback mode.
 * @freq: the transfer speed in Hz.
 * @word_delay_ns: delay to be inserted between consecutive words of a
 *     transfer, in ns unit.
 * @cs_setup_ns: delay to be introduced after CS is asserted, in ns
 *     unit.
 * @cs_delay_hold_ns: delay to be introduced before CS is deasserted
 *     for each transfer, in ns unit.
 * @cs_change_delay_inactive_ns: delay to be introduced after CS is
 *     deasserted and before next asserted, in ns unit.
 */
struct spi_transfer_head {
	__u8 chip_select_id;
	__u8 bits_per_word;
	__u8 cs_change;
	__u8 tx_nbits;
	__u8 rx_nbits;
	__u8 reserved[3];
	__le32 mode;
	__le32 freq;
	__le32 word_delay_ns;
	__le32 cs_setup_ns;
	__le32 cs_delay_hold_ns;
	__le32 cs_change_delay_inactive_ns;
};

/**
 * struct spi_transfer_result - virtio SPI transfer result
 * @result: Transfer result code.

Annotation

Implementation Notes