lib/raid/raid6/loongarch/loongarch_simd.c

Source file repositories/reference/linux-study-clean/lib/raid/raid6/loongarch/loongarch_simd.c

File Facts

System
Linux kernel
Corpus path
lib/raid/raid6/loongarch/loongarch_simd.c
Extension
.c
Size
13530 bytes
Lines
410
Domain
Kernel Services
Bucket
lib
Inferred role
Kernel Services: implementation source
Status
source implementation candidate

Why This File Exists

Shared kernel service surface used by multiple subsystems, including helpers, cryptography, virtualization support, and async I/O infrastructure.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * RAID6 syndrome calculations in LoongArch SIMD (LSX & LASX)
 *
 * Copyright 2023 WANG Xuerui <git@xen0n.name>
 *
 * Based on the generic RAID-6 code (int.uc):
 *
 * Copyright 2002-2004 H. Peter Anvin
 */

#include <asm/cpu-features.h>
#include <asm/fpu.h>
#include "algos.h"

/*
 * The vector algorithms are currently priority 0, which means the generic
 * scalar algorithms are not being disabled if vector support is present.
 * This is like the similar LoongArch RAID5 XOR code, with the main reason
 * repeated here: it cannot be ruled out at this point of time, that some
 * future (maybe reduced) models could run the vector algorithms slower than
 * the scalar ones, maybe for errata or micro-op reasons. It may be
 * appropriate to revisit this after one or two more uarch generations.
 */

#ifdef CONFIG_CPU_HAS_LSX
#define NSIZE 16

static void raid6_lsx_gen_syndrome(int disks, size_t bytes, void **ptrs)
{
	u8 **dptr = (u8 **)ptrs;
	u8 *p, *q;
	int d, z, z0;

	z0 = disks - 3;		/* Highest data disk */
	p = dptr[z0+1];		/* XOR parity */
	q = dptr[z0+2];		/* RS syndrome */

	kernel_fpu_begin();

	/*
	 * $vr0, $vr1, $vr2, $vr3: wp
	 * $vr4, $vr5, $vr6, $vr7: wq
	 * $vr8, $vr9, $vr10, $vr11: wd
	 * $vr12, $vr13, $vr14, $vr15: w2
	 * $vr16, $vr17, $vr18, $vr19: w1
	 */
	for (d = 0; d < bytes; d += NSIZE*4) {
		/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
		asm volatile("vld $vr0, %0" : : "m"(dptr[z0][d+0*NSIZE]));
		asm volatile("vld $vr1, %0" : : "m"(dptr[z0][d+1*NSIZE]));
		asm volatile("vld $vr2, %0" : : "m"(dptr[z0][d+2*NSIZE]));
		asm volatile("vld $vr3, %0" : : "m"(dptr[z0][d+3*NSIZE]));
		asm volatile("vori.b $vr4, $vr0, 0");
		asm volatile("vori.b $vr5, $vr1, 0");
		asm volatile("vori.b $vr6, $vr2, 0");
		asm volatile("vori.b $vr7, $vr3, 0");
		for (z = z0-1; z >= 0; z--) {
			/* wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE]; */
			asm volatile("vld $vr8, %0" : : "m"(dptr[z][d+0*NSIZE]));
			asm volatile("vld $vr9, %0" : : "m"(dptr[z][d+1*NSIZE]));
			asm volatile("vld $vr10, %0" : : "m"(dptr[z][d+2*NSIZE]));
			asm volatile("vld $vr11, %0" : : "m"(dptr[z][d+3*NSIZE]));
			/* wp$$ ^= wd$$; */
			asm volatile("vxor.v $vr0, $vr0, $vr8");
			asm volatile("vxor.v $vr1, $vr1, $vr9");
			asm volatile("vxor.v $vr2, $vr2, $vr10");
			asm volatile("vxor.v $vr3, $vr3, $vr11");
			/* w2$$ = MASK(wq$$); */
			asm volatile("vslti.b $vr12, $vr4, 0");
			asm volatile("vslti.b $vr13, $vr5, 0");
			asm volatile("vslti.b $vr14, $vr6, 0");
			asm volatile("vslti.b $vr15, $vr7, 0");
			/* w1$$ = SHLBYTE(wq$$); */
			asm volatile("vslli.b $vr16, $vr4, 1");
			asm volatile("vslli.b $vr17, $vr5, 1");
			asm volatile("vslli.b $vr18, $vr6, 1");
			asm volatile("vslli.b $vr19, $vr7, 1");
			/* w2$$ &= NBYTES(0x1d); */
			asm volatile("vandi.b $vr12, $vr12, 0x1d");
			asm volatile("vandi.b $vr13, $vr13, 0x1d");
			asm volatile("vandi.b $vr14, $vr14, 0x1d");
			asm volatile("vandi.b $vr15, $vr15, 0x1d");
			/* w1$$ ^= w2$$; */
			asm volatile("vxor.v $vr16, $vr16, $vr12");
			asm volatile("vxor.v $vr17, $vr17, $vr13");
			asm volatile("vxor.v $vr18, $vr18, $vr14");
			asm volatile("vxor.v $vr19, $vr19, $vr15");
			/* wq$$ = w1$$ ^ wd$$; */
			asm volatile("vxor.v $vr4, $vr16, $vr8");

Annotation

Implementation Notes