rust/kernel/net/phy/reg.rs
Source file repositories/reference/linux-study-clean/rust/kernel/net/phy/reg.rs
File Facts
- System
- Linux kernel
- Corpus path
rust/kernel/net/phy/reg.rs- Extension
.rs- Size
- 7653 bytes
- Lines
- 227
- Domain
- Rust Kernel Layer
- Bucket
- Rust API Membrane
- Inferred role
- Rust Kernel Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
Rust-side wrappers and abstractions around kernel C APIs, ownership contracts, allocation, synchronization, and module integration.
- Rust-side wrappers and abstractions around kernel C APIs, ownership contracts, allocation, synchronization, and module integration.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2024 FUJITA Tomonori <fujita.tomonori@gmail.com>
//! PHY register interfaces.
//!
//! This module provides support for accessing PHY registers in the
//! Ethernet management interface clauses 22 and 45 register namespaces, as
//! defined in IEEE 802.3.
use super::Device;
use crate::{
build_assert::build_assert,
error::*,
uapi, //
};
mod private {
/// Marker that a trait cannot be implemented outside of this crate
pub trait Sealed {}
}
/// Accesses PHY registers.
///
/// This trait is used to implement the unified interface to access
/// C22 and C45 PHY registers.
///
/// # Examples
///
/// ```ignore
/// fn link_change_notify(dev: &mut Device) {
/// // read C22 BMCR register
/// dev.read(C22::BMCR);
/// // read C45 PMA/PMD control 1 register
/// dev.read(C45::new(Mmd::PMAPMD, 0));
///
/// // Checks the link status as reported by registers in the C22 namespace
/// // and updates current link state.
/// dev.genphy_read_status::<phy::C22>();
/// // Checks the link status as reported by registers in the C45 namespace
/// // and updates current link state.
/// dev.genphy_read_status::<phy::C45>();
/// }
/// ```
pub trait Register: private::Sealed {
/// Reads a PHY register.
fn read(&self, dev: &mut Device) -> Result<u16>;
/// Writes a PHY register.
fn write(&self, dev: &mut Device, val: u16) -> Result;
/// Checks the link status and updates current link state.
fn read_status(dev: &mut Device) -> Result<u16>;
}
/// A single MDIO clause 22 register address (5 bits).
#[derive(Copy, Clone, Debug)]
pub struct C22(u8);
impl C22 {
/// Basic mode control.
pub const BMCR: Self = C22(0x00);
/// Basic mode status.
pub const BMSR: Self = C22(0x01);
/// PHY identifier 1.
pub const PHYSID1: Self = C22(0x02);
/// PHY identifier 2.
pub const PHYSID2: Self = C22(0x03);
/// Auto-negotiation advertisement.
pub const ADVERTISE: Self = C22(0x04);
/// Auto-negotiation link partner base page ability.
pub const LPA: Self = C22(0x05);
/// Auto-negotiation expansion.
pub const EXPANSION: Self = C22(0x06);
/// Auto-negotiation next page transmit.
pub const NEXT_PAGE_TRANSMIT: Self = C22(0x07);
/// Auto-negotiation link partner received next page.
pub const LP_RECEIVED_NEXT_PAGE: Self = C22(0x08);
/// Master-slave control.
pub const MASTER_SLAVE_CONTROL: Self = C22(0x09);
/// Master-slave status.
pub const MASTER_SLAVE_STATUS: Self = C22(0x0a);
/// PSE Control.
pub const PSE_CONTROL: Self = C22(0x0b);
/// PSE Status.
pub const PSE_STATUS: Self = C22(0x0c);
/// MMD Register control.
pub const MMD_CONTROL: Self = C22(0x0d);
/// MMD Register address data.
pub const MMD_DATA: Self = C22(0x0e);
Annotation
- Atlas domain: Rust Kernel Layer / Rust API Membrane.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.