rust/kernel/pci/io.rs

Source file repositories/reference/linux-study-clean/rust/kernel/pci/io.rs

File Facts

System
Linux kernel
Corpus path
rust/kernel/pci/io.rs
Extension
.rs
Size
10975 bytes
Lines
312
Domain
Rust Kernel Layer
Bucket
Rust API Membrane
Inferred role
Rust Kernel Layer: implementation source
Status
source implementation candidate

Why This File Exists

Rust-side wrappers and abstractions around kernel C APIs, ownership contracts, allocation, synchronization, and module integration.

Dependency Surface

Detected Declarations

Annotated Snippet

unsafe fn io_write(&self, value: $ty, address: usize) {
                // Return value from C function is ignored in infallible accessors.
                let _ret =
                    // SAFETY: By the type invariant `self.pdev` is a valid address.
                    // CAST: The offset is cast to `i32` because the C functions expect a 32-bit
                    // signed offset parameter. PCI configuration space size is at most 4096 bytes,
                    // so the value always fits within `i32` without truncation or sign change.
                    unsafe { bindings::$write_fn(self.pdev.as_raw(), address as i32, value) };
            }
        }
    };
}

// PCI configuration space supports 8, 16, and 32-bit accesses.
impl_config_space_io_capable!(u8, pci_read_config_byte, pci_write_config_byte);
impl_config_space_io_capable!(u16, pci_read_config_word, pci_write_config_word);
impl_config_space_io_capable!(u32, pci_read_config_dword, pci_write_config_dword);

impl<'a, S: ConfigSpaceKind> Io for ConfigSpace<'a, S> {
    /// Returns the base address of the I/O region. It is always 0 for configuration space.
    #[inline]
    fn addr(&self) -> usize {
        0
    }

    /// Returns the maximum size of the configuration space.
    #[inline]
    fn maxsize(&self) -> usize {
        self.pdev.cfg_size().into_raw()
    }
}

impl<'a, S: ConfigSpaceKind> IoKnownSize for ConfigSpace<'a, S> {
    const MIN_SIZE: usize = S::SIZE;
}

/// A PCI BAR to perform I/O-Operations on.
///
/// I/O backend assumes that the device is little-endian and will automatically
/// convert from little-endian to CPU endianness.
///
/// # Invariants
///
/// `Bar` always holds an `IoRaw` instance that holds a valid pointer to the start of the I/O
/// memory mapped PCI BAR and its size.
pub struct Bar<'a, const SIZE: usize = 0> {
    pdev: &'a Device<device::Bound>,
    io: MmioRaw<SIZE>,
    num: i32,
}

impl<'a, const SIZE: usize> Bar<'a, SIZE> {
    pub(super) fn new(
        pdev: &'a Device<device::Bound>,
        num: u32,
        name: &'static CStr,
    ) -> Result<Self> {
        let len = pdev.resource_len(num)?;
        if len == 0 {
            return Err(ENOMEM);
        }

        // Convert to `i32`, since that's what all the C bindings use.
        let num = i32::try_from(num)?;

        // SAFETY:
        // `pdev` is valid by the invariants of `Device`.
        // `num` is checked for validity by a previous call to `Device::resource_len`.
        // `name` is always valid.
        let ret = unsafe { bindings::pci_request_region(pdev.as_raw(), num, name.as_char_ptr()) };
        if ret != 0 {
            return Err(EBUSY);
        }

        // SAFETY:
        // `pdev` is valid by the invariants of `Device`.
        // `num` is checked for validity by a previous call to `Device::resource_len`.
        // `name` is always valid.
        let ioptr: usize = unsafe { bindings::pci_iomap(pdev.as_raw(), num, 0) } as usize;
        if ioptr == 0 {
            // SAFETY:
            // `pdev` is valid by the invariants of `Device`.
            // `num` is checked for validity by a previous call to `Device::resource_len`.
            unsafe { bindings::pci_release_region(pdev.as_raw(), num) };
            return Err(ENOMEM);
        }

        let io = match MmioRaw::new(ioptr, len as usize) {
            Ok(io) => io,
            Err(err) => {

Annotation

Implementation Notes