rust/zerocopy/benches/new_vec_zeroed.x86-64.mca

File Facts

System

Linux kernel

Corpus path

rust/zerocopy/benches/new_vec_zeroed.x86-64.mca

Extension

.mca

Size

5767 bytes

Lines

114

Domain

Rust Kernel Layer

Bucket

Rust API Membrane

Inferred role

Rust Kernel Layer: Rust API Membrane

Status

atlas-only

Why This File Exists

Rust-side wrappers and abstractions around kernel C APIs, ownership contracts, allocation, synchronization, and module integration.

• Rust-side wrappers and abstractions around kernel C APIs, ownership contracts, allocation, synchronization, and module integration.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

Iterations:        100
Instructions:      3700
Total Cycles:      3486
Total uOps:        4600

Dispatch Width:    4
uOps Per Cycle:    1.32
IPC:               1.06
Block RThroughput: 12.0


Instruction Info:
[1]: #uOps
[2]: Latency
[3]: RThroughput
[4]: MayLoad
[5]: MayStore
[6]: HasSideEffects (U)

[1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 1      1     0.33                        mov	rax, rdi
 1      1     0.33                        movabs	rcx, 1537228672809129301
 1      1     0.33                        cmp	rsi, rcx
 1      1     1.00                        ja	.LBB5_5
 1      1     0.33                        test	rsi, rsi
 1      1     1.00                        je	.LBB5_2
 2      5     1.00           *            push	r15
 2      5     1.00           *            push	r14
 2      5     1.00           *            push	rbx
 1      1     0.50                        lea	rcx, [rsi + rsi]
 1      1     0.50                        lea	rbx, [rcx + 2*rcx]
 1      1     0.33                        mov	r14, rax
 1      1     0.33                        mov	r15, rsi
 4      7     1.00    *                   call	qword ptr [rip + __rustc::__rust_no_alloc_shim_is_unstable_v2@GOTPCREL]
 1      1     0.33                        mov	esi, 2
 1      1     0.33                        mov	rdi, rbx
 4      7     1.00    *                   call	qword ptr [rip + __rustc::__rust_alloc_zeroed@GOTPCREL]
 1      1     0.33                        mov	rsi, r15
 1      1     0.33                        mov	rcx, rax
 1      1     0.33                        mov	rax, r14
 1      1     0.33                        test	rcx, rcx
 1      6     0.50    *                   pop	rbx
 1      6     0.50    *                   pop	r14
 1      6     0.50    *                   pop	r15
 1      1     1.00                        je	.LBB5_5
 1      1     1.00           *            mov	qword ptr [rax], rsi
 1      1     1.00           *            mov	qword ptr [rax + 8], rcx
 1      1     1.00           *            mov	qword ptr [rax + 16], rsi
 1      1     1.00                  U     ret
 1      1     0.33                        movabs	rcx, -9223372036854775808
 1      1     1.00           *            mov	qword ptr [rax], rcx
 1      1     1.00                  U     ret
 1      1     0.33                        mov	ecx, 2
 1      1     1.00           *            mov	qword ptr [rax], rsi
 1      1     1.00           *            mov	qword ptr [rax + 8], rcx
 1      1     1.00           *            mov	qword ptr [rax + 16], rsi
 1      1     1.00                  U     ret


Resources:
[0]   - SBDivider
[1]   - SBFPDivider
[2]   - SBPort0
[3]   - SBPort1
[4]   - SBPort4
[5]   - SBPort5
[6.0] - SBPort23
[6.1] - SBPort23

Annotation

• Atlas domain: Rust Kernel Layer / Rust API Membrane.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.