sound/hda/codecs/ca0132_regs.h

Source file repositories/reference/linux-study-clean/sound/hda/codecs/ca0132_regs.h

File Facts

System
Linux kernel
Corpus path
sound/hda/codecs/ca0132_regs.h
Extension
.h
Size
13680 bytes
Lines
397
Domain
Driver Families
Bucket
sound/hda
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __CA0132_REGS_H
#define __CA0132_REGS_H

#define DSP_CHIP_OFFSET                0x100000
#define DSP_DBGCNTL_MODULE_OFFSET      0xE30
#define DSP_DBGCNTL_INST_OFFSET \
	(DSP_CHIP_OFFSET + DSP_DBGCNTL_MODULE_OFFSET)

#define DSP_DBGCNTL_EXEC_LOBIT         0x0
#define DSP_DBGCNTL_EXEC_HIBIT         0x3
#define DSP_DBGCNTL_EXEC_MASK          0xF

#define DSP_DBGCNTL_SS_LOBIT           0x4
#define DSP_DBGCNTL_SS_HIBIT           0x7
#define DSP_DBGCNTL_SS_MASK            0xF0

#define DSP_DBGCNTL_STATE_LOBIT        0xA
#define DSP_DBGCNTL_STATE_HIBIT        0xD
#define DSP_DBGCNTL_STATE_MASK         0x3C00

#define XRAM_CHIP_OFFSET               0x0
#define XRAM_XRAM_CHANNEL_COUNT        0xE000
#define XRAM_XRAM_MODULE_OFFSET        0x0
#define XRAM_XRAM_CHAN_INCR            4
#define XRAM_XRAM_INST_OFFSET(_chan) \
	(XRAM_CHIP_OFFSET + XRAM_XRAM_MODULE_OFFSET + \
	(_chan * XRAM_XRAM_CHAN_INCR))

#define YRAM_CHIP_OFFSET               0x40000
#define YRAM_YRAM_CHANNEL_COUNT        0x8000
#define YRAM_YRAM_MODULE_OFFSET        0x0
#define YRAM_YRAM_CHAN_INCR            4
#define YRAM_YRAM_INST_OFFSET(_chan) \
	(YRAM_CHIP_OFFSET + YRAM_YRAM_MODULE_OFFSET + \
	(_chan * YRAM_YRAM_CHAN_INCR))

#define UC_CHIP_OFFSET                 0x80000
#define UC_UC_CHANNEL_COUNT            0x10000
#define UC_UC_MODULE_OFFSET            0x0
#define UC_UC_CHAN_INCR                4
#define UC_UC_INST_OFFSET(_chan) \
	(UC_CHIP_OFFSET + UC_UC_MODULE_OFFSET + \
	(_chan * UC_UC_CHAN_INCR))

#define AXRAM_CHIP_OFFSET              0x3C000
#define AXRAM_AXRAM_CHANNEL_COUNT      0x1000
#define AXRAM_AXRAM_MODULE_OFFSET      0x0
#define AXRAM_AXRAM_CHAN_INCR          4
#define AXRAM_AXRAM_INST_OFFSET(_chan) \
	(AXRAM_CHIP_OFFSET + AXRAM_AXRAM_MODULE_OFFSET + \
	(_chan * AXRAM_AXRAM_CHAN_INCR))

#define AYRAM_CHIP_OFFSET              0x78000
#define AYRAM_AYRAM_CHANNEL_COUNT      0x1000
#define AYRAM_AYRAM_MODULE_OFFSET      0x0
#define AYRAM_AYRAM_CHAN_INCR          4
#define AYRAM_AYRAM_INST_OFFSET(_chan) \
	(AYRAM_CHIP_OFFSET + AYRAM_AYRAM_MODULE_OFFSET + \
	(_chan * AYRAM_AYRAM_CHAN_INCR))

#define DSPDMAC_CHIP_OFFSET            0x110000
#define DSPDMAC_DMA_CFG_CHANNEL_COUNT  12
#define DSPDMAC_DMACFG_MODULE_OFFSET   0xF00
#define DSPDMAC_DMACFG_CHAN_INCR       0x10
#define DSPDMAC_DMACFG_INST_OFFSET(_chan) \
	(DSPDMAC_CHIP_OFFSET + DSPDMAC_DMACFG_MODULE_OFFSET + \
	(_chan * DSPDMAC_DMACFG_CHAN_INCR))

#define DSPDMAC_DMACFG_DBADR_LOBIT     0x0
#define DSPDMAC_DMACFG_DBADR_HIBIT     0x10
#define DSPDMAC_DMACFG_DBADR_MASK      0x1FFFF
#define DSPDMAC_DMACFG_LP_LOBIT        0x11
#define DSPDMAC_DMACFG_LP_HIBIT        0x11
#define DSPDMAC_DMACFG_LP_MASK         0x20000

#define DSPDMAC_DMACFG_AINCR_LOBIT     0x12
#define DSPDMAC_DMACFG_AINCR_HIBIT     0x12
#define DSPDMAC_DMACFG_AINCR_MASK      0x40000

#define DSPDMAC_DMACFG_DWR_LOBIT       0x13
#define DSPDMAC_DMACFG_DWR_HIBIT       0x13
#define DSPDMAC_DMACFG_DWR_MASK        0x80000

#define DSPDMAC_DMACFG_AJUMP_LOBIT     0x14
#define DSPDMAC_DMACFG_AJUMP_HIBIT     0x17
#define DSPDMAC_DMACFG_AJUMP_MASK      0xF00000

#define DSPDMAC_DMACFG_AMODE_LOBIT     0x18
#define DSPDMAC_DMACFG_AMODE_HIBIT     0x19
#define DSPDMAC_DMACFG_AMODE_MASK      0x3000000

Annotation

Implementation Notes