sound/hda/codecs/side-codecs/cs35l41_hda.c

Source file repositories/reference/linux-study-clean/sound/hda/codecs/side-codecs/cs35l41_hda.c

File Facts

System
Linux kernel
Corpus path
sound/hda/codecs/side-codecs/cs35l41_hda.c
Extension
.c
Size
59349 bytes
Lines
2131
Domain
Driver Families
Bucket
sound/hda
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cs35l41_tuning_param_hdr {
	__le32 tuning_index;
	__le32 type;
	__le32 size;
} __packed;

struct cs35l41_tuning_param {
	struct cs35l41_tuning_param_hdr hdr;
	union {
		__le32 gain;
	};
} __packed;

struct cs35l41_tuning_params {
	__le32 signature;
	__le32 version;
	__le32 size;
	__le32 num_entries;
	u8 data[];
} __packed;

/* Firmware calibration controls */
static const struct cirrus_amp_cal_controls cs35l41_calibration_controls = {
	.alg_id =	CAL_DSP_CTL_ALG,
	.mem_region =	CAL_DSP_CTL_TYPE,
	.ambient =	CAL_AMBIENT_DSP_CTL_NAME,
	.calr =		CAL_R_DSP_CTL_NAME,
	.status =	CAL_STATUS_DSP_CTL_NAME,
	.checksum =	CAL_CHECKSUM_DSP_CTL_NAME,
};

enum cs35l41_hda_fw_id {
	CS35L41_HDA_FW_SPK_PROT,
	CS35L41_HDA_FW_SPK_CALI,
	CS35L41_HDA_FW_SPK_DIAG,
	CS35L41_HDA_FW_MISC,
	CS35L41_HDA_NUM_FW
};

static const char * const cs35l41_hda_fw_ids[CS35L41_HDA_NUM_FW] = {
	[CS35L41_HDA_FW_SPK_PROT] = "spk-prot",
	[CS35L41_HDA_FW_SPK_CALI] = "spk-cali",
	[CS35L41_HDA_FW_SPK_DIAG] = "spk-diag",
	[CS35L41_HDA_FW_MISC] =     "misc",
};

static bool firmware_autostart = 1;
module_param(firmware_autostart, bool, 0444);
MODULE_PARM_DESC(firmware_autostart, "Allow automatic firmware download on boot"
			     "(0=Disable, 1=Enable) (default=1); ");

static const char channel_name[3] = { 'L', 'R', 'C' };

static const struct reg_sequence cs35l41_hda_config[] = {
	{ CS35L41_PLL_CLK_CTRL,		0x00000430 }, // 3072000Hz, BCLK Input, PLL_REFCLK_EN = 1
	{ CS35L41_DSP_CLK_CTRL,		0x00000003 }, // DSP CLK EN
	{ CS35L41_GLOBAL_CLK_CTRL,	0x00000003 }, // GLOBAL_FS = 48 kHz
	{ CS35L41_SP_RATE_CTRL,		0x00000021 }, // ASP_BCLK_FREQ = 3.072 MHz
	{ CS35L41_SP_FORMAT,		0x20200200 }, // 32 bits RX/TX slots, I2S, clk consumer
	{ CS35L41_SP_TX_WL,		0x00000018 }, // 24 cycles/slot
	{ CS35L41_SP_RX_WL,		0x00000018 }, // 24 cycles/slot
	{ CS35L41_ASP_TX1_SRC,		0x00000018 }, // ASPTX1 SRC = VMON
	{ CS35L41_ASP_TX2_SRC,		0x00000019 }, // ASPTX2 SRC = IMON
	{ CS35L41_DSP1_RX3_SRC,         0x00000018 }, // DSP1RX3 SRC = VMON
	{ CS35L41_DSP1_RX4_SRC,         0x00000019 }, // DSP1RX4 SRC = IMON
};

static const struct reg_sequence cs35l41_hda_config_no_dsp[] = {
	{ CS35L41_SP_HIZ_CTRL,		0x00000002 }, // Hi-Z unused
	{ CS35L41_DAC_PCM1_SRC,		0x00000008 }, // DACPCM1_SRC = ASPRX1
	{ CS35L41_ASP_TX3_SRC,		0x00000000 }, // ASPTX3 SRC = ZERO FILL
	{ CS35L41_ASP_TX4_SRC,		0x00000000 }, // ASPTX4 SRC = ZERO FILL
	{ CS35L41_DSP1_RX5_SRC,         0x00000020 }, // DSP1RX5 SRC = ERRVOL
	{ CS35L41_DSP1_RX6_SRC,         0x00000021 }, // DSP1RX6 SRC = CLASSH_TGT
};

static const struct reg_sequence cs35l41_hda_config_dsp[] = {
	{ CS35L41_SP_HIZ_CTRL,		0x00000003 }, // Hi-Z unused/disabled
	{ CS35L41_DAC_PCM1_SRC,		0x00000032 }, // DACPCM1_SRC = DSP1TX1
	{ CS35L41_ASP_TX3_SRC,		0x00000028 }, // ASPTX3 SRC = VPMON
	{ CS35L41_ASP_TX4_SRC,		0x00000029 }, // ASPTX4 SRC = VBSTMON
	{ CS35L41_DSP1_RX6_SRC,         0x00000029 }, // DSP1RX6 SRC = VBSTMON
};

static const struct reg_sequence cs35l41_hda_unmute[] = {
	{ CS35L41_AMP_DIG_VOL_CTRL,	0x00008000 }, // AMP_HPF_PCM_EN = 1, AMP_VOL_PCM  0.0 dB
	{ CS35L41_AMP_GAIN_CTRL,	0x00000084 }, // AMP_GAIN_PCM 4.5 dB
};

static const struct reg_sequence cs35l41_hda_mute[] = {

Annotation

Implementation Notes