sound/pci/ad1889.h

Source file repositories/reference/linux-study-clean/sound/pci/ad1889.h

File Facts

System: Linux kernel
Corpus path: sound/pci/ad1889.h
Extension: .h
Size: 8112 bytes
Lines: 191
Domain: Driver Families
Bucket: sound/pci
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __AD1889_H__
#define __AD1889_H__

#define AD_DS_WSMC	0x00 /* wave/synthesis channel mixer control */
#define  AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
#define  AD_DS_WSMC_SYRQ 0x0030 /* synth. fifo request point */
#define  AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
#define  AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
#define  AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
#define  AD_DS_WSMC_WARQ 0x3000 /* wave fifo request point */

#define AD_DS_RAMC	0x02 /* resampler/ADC channel mixer control */
#define  AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
#define  AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
#define  AD_DS_RAMC_ADEN 0x0004 /* ADC channel enable */
#define  AD_DS_RAMC_ACRQ 0x0030 /* ADC fifo request point */
#define  AD_DS_RAMC_REEN 0x0400 /* resampler channel enable */
#define  AD_DS_RAMC_RERQ 0x3000 /* res. fifo request point */

#define AD_DS_WADA	0x04 /* wave channel mix attenuation */
#define  AD_DS_WADA_RWAM 0x0080 /* right wave mute */
#define  AD_DS_WADA_RWAA 0x001f /* right wave attenuation */
#define  AD_DS_WADA_LWAM 0x8000 /* left wave mute */
#define  AD_DS_WADA_LWAA 0x3e00 /* left wave attenuation */

#define AD_DS_SYDA	0x06 /* synthesis channel mix attenuation */
#define  AD_DS_SYDA_RSYM 0x0080 /* right synthesis mute */
#define  AD_DS_SYDA_RSYA 0x001f /* right synthesis attenuation */
#define  AD_DS_SYDA_LSYM 0x8000 /* left synthesis mute */
#define  AD_DS_SYDA_LSYA 0x3e00 /* left synthesis attenuation */

#define AD_DS_WAS	0x08 /* wave channel sample rate */
#define  AD_DS_WAS_WAS   0xffff /* sample rate mask */

#define AD_DS_RES	0x0a /* resampler channel sample rate */
#define  AD_DS_RES_RES   0xffff /* sample rate mask */

#define AD_DS_CCS	0x0c /* chip control/status */
#define  AD_DS_CCS_ADO   0x0001 /* ADC channel overflow */
#define  AD_DS_CCS_REO   0x0002 /* resampler channel overflow */
#define  AD_DS_CCS_SYU   0x0004 /* synthesis channel underflow */
#define  AD_DS_CCS_WAU   0x0008 /* wave channel underflow */
/* bits 4 -> 7, 9, 11 -> 14 reserved */
#define  AD_DS_CCS_XTD   0x0100 /* xtd delay control (4096 clock cycles) */
#define  AD_DS_CCS_PDALL 0x0400 /* power */
#define  AD_DS_CCS_CLKEN 0x8000 /* clock */

#define AD_DMA_RESBA	0x40 /* RES base address */
#define AD_DMA_RESCA	0x44 /* RES current address */
#define AD_DMA_RESBC	0x48 /* RES base count */
#define AD_DMA_RESCC	0x4c /* RES current count */

#define AD_DMA_ADCBA	0x50 /* ADC base address */
#define AD_DMA_ADCCA	0x54 /* ADC current address */
#define AD_DMA_ADCBC	0x58 /* ADC base count */
#define AD_DMA_ADCCC	0x5c /* ADC current count */

#define AD_DMA_SYNBA	0x60 /* synth base address */
#define AD_DMA_SYNCA	0x64 /* synth current address */
#define AD_DMA_SYNBC	0x68 /* synth base count */
#define AD_DMA_SYNCC	0x6c /* synth current count */

#define AD_DMA_WAVBA	0x70 /* wave base address */
#define AD_DMA_WAVCA	0x74 /* wave current address */
#define AD_DMA_WAVBC	0x78 /* wave base count */
#define AD_DMA_WAVCC	0x7c /* wave current count */

#define AD_DMA_RESIC	0x80 /* RES dma interrupt current byte count */
#define AD_DMA_RESIB	0x84 /* RES dma interrupt base byte count */

#define AD_DMA_ADCIC	0x88 /* ADC dma interrupt current byte count */
#define AD_DMA_ADCIB	0x8c /* ADC dma interrupt base byte count */

#define AD_DMA_SYNIC	0x90 /* synth dma interrupt current byte count */
#define AD_DMA_SYNIB	0x94 /* synth dma interrupt base byte count */

#define AD_DMA_WAVIC	0x98 /* wave dma interrupt current byte count */
#define AD_DMA_WAVIB	0x9c /* wave dma interrupt base byte count */

#define  AD_DMA_ICC	0xffffff /* current byte count mask */
#define  AD_DMA_IBC	0xffffff /* base byte count mask */
/* bits 24 -> 31 reserved */

/* 4 bytes pad */
#define AD_DMA_ADC	0xa8	/* ADC      dma control and status */
#define AD_DMA_SYNTH	0xb0	/* Synth    dma control and status */
#define AD_DMA_WAV	0xb8	/* wave     dma control and status */
#define AD_DMA_RES	0xa0	/* Resample dma control and status */

#define  AD_DMA_SGDE	0x0001 /* SGD mode enable */

Annotation

Atlas domain: Driver Families / sound/pci.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.