sound/pci/ice1712/envy24ht.h

Source file repositories/reference/linux-study-clean/sound/pci/ice1712/envy24ht.h

File Facts

System
Linux kernel
Corpus path
sound/pci/ice1712/envy24ht.h
Extension
.h
Size
8688 bytes
Lines
207
Domain
Driver Families
Bucket
sound/pci
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SOUND_VT1724_H
#define __SOUND_VT1724_H

/*
 *   ALSA driver for ICEnsemble VT1724 (Envy24)
 *
 *	Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
 */      

#include <sound/control.h>
#include <sound/ac97_codec.h>
#include <sound/rawmidi.h>
#include <sound/i2c.h>
#include <sound/pcm.h>

#include "ice1712.h"

enum {
	ICE_EEP2_SYSCONF = 0,	/* 06 */
	ICE_EEP2_ACLINK,	/* 07 */
	ICE_EEP2_I2S,		/* 08 */
	ICE_EEP2_SPDIF,		/* 09 */
	ICE_EEP2_GPIO_DIR,	/* 0a */
	ICE_EEP2_GPIO_DIR1,	/* 0b */
	ICE_EEP2_GPIO_DIR2,	/* 0c */
	ICE_EEP2_GPIO_MASK,	/* 0d */
	ICE_EEP2_GPIO_MASK1,	/* 0e */
	ICE_EEP2_GPIO_MASK2,	/* 0f */
	ICE_EEP2_GPIO_STATE,	/* 10 */
	ICE_EEP2_GPIO_STATE1,	/* 11 */
	ICE_EEP2_GPIO_STATE2	/* 12 */
};
	
/*
 *  Direct registers
 */

#define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)

#define VT1724_REG_CONTROL		0x00	/* byte */
#define   VT1724_RESET			0x80	/* reset whole chip */
#define VT1724_REG_IRQMASK		0x01	/* byte */
#define   VT1724_IRQ_MPU_RX		0x80
#define   VT1724_IRQ_MPU_TX		0x20
#define   VT1724_IRQ_MTPCM		0x10
#define VT1724_REG_IRQSTAT		0x02	/* byte */
/* look to VT1724_IRQ_* */
#define VT1724_REG_SYS_CFG		0x04	/* byte - system configuration PCI60 on Envy24*/
#define   VT1724_CFG_CLOCK	0xc0
#define     VT1724_CFG_CLOCK512	0x00	/* 22.5692Mhz, 44.1kHz*512 */
#define     VT1724_CFG_CLOCK384  0x40	/* 16.9344Mhz, 44.1kHz*384 */
#define   VT1724_CFG_MPU401	0x20		/* MPU401 UARTs */
#define   VT1724_CFG_ADC_MASK	0x0c	/* one, two or one and S/PDIF, stereo ADCs */
#define   VT1724_CFG_ADC_NONE	0x0c	/* no ADCs */
#define   VT1724_CFG_DAC_MASK	0x03	/* one, two, three, four stereo DACs */

#define VT1724_REG_AC97_CFG		0x05	/* byte */
#define   VT1724_CFG_PRO_I2S	0x80	/* multitrack converter: I2S or AC'97 */
#define   VT1724_CFG_AC97_PACKED	0x01	/* split or packed mode - AC'97 */

#define VT1724_REG_I2S_FEATURES		0x06	/* byte */
#define   VT1724_CFG_I2S_VOLUME	0x80	/* volume/mute capability */
#define   VT1724_CFG_I2S_96KHZ	0x40	/* supports 96kHz sampling */
#define   VT1724_CFG_I2S_RESMASK	0x30	/* resolution mask, 16,18,20,24-bit */
#define   VT1724_CFG_I2S_192KHZ	0x08	/* supports 192kHz sampling */
#define   VT1724_CFG_I2S_OTHER	0x07	/* other I2S IDs */

#define VT1724_REG_SPDIF_CFG		0x07	/* byte */
#define   VT1724_CFG_SPDIF_OUT_EN	0x80	/*Internal S/PDIF output is enabled*/
#define   VT1724_CFG_SPDIF_OUT_INT	0x40	/*Internal S/PDIF output is implemented*/
#define   VT1724_CFG_I2S_CHIPID	0x3c	/* I2S chip ID */
#define   VT1724_CFG_SPDIF_IN	0x02	/* S/PDIF input is present */
#define   VT1724_CFG_SPDIF_OUT	0x01	/* External S/PDIF output is present */

/*there is no consumer AC97 codec with the VT1724*/
//#define VT1724_REG_AC97_INDEX		0x08	/* byte */
//#define VT1724_REG_AC97_CMD		0x09	/* byte */

#define VT1724_REG_MPU_TXFIFO		0x0a	/*byte ro. number of bytes in TX fifo*/
#define VT1724_REG_MPU_RXFIFO		0x0b	/*byte ro. number of bytes in RX fifo*/

#define VT1724_REG_MPU_DATA		0x0c	/* byte */
#define VT1724_REG_MPU_CTRL		0x0d	/* byte */
#define   VT1724_MPU_UART	0x01
#define   VT1724_MPU_TX_EMPTY	0x02
#define   VT1724_MPU_TX_FULL	0x04
#define   VT1724_MPU_RX_EMPTY	0x08
#define   VT1724_MPU_RX_FULL	0x10

#define VT1724_REG_MPU_FIFO_WM	0x0e	/*byte set the high/low watermarks for RX/TX fifos*/

Annotation

Implementation Notes