sound/pci/ice1712/quartet.c

Source file repositories/reference/linux-study-clean/sound/pci/ice1712/quartet.c

File Facts

System
Linux kernel
Corpus path
sound/pci/ice1712/quartet.c
Extension
.c
Size
28714 bytes
Lines
1070
Domain
Driver Families
Bucket
sound/pci
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct qtet_spec {
	struct ak4113 *ak4113;
	unsigned int scr;	/* system control register */
	unsigned int mcr;	/* monitoring control register */
	unsigned int cpld;	/* cpld register */
};

struct qtet_kcontrol_private {
	unsigned int bit;
	void (*set_register)(struct snd_ice1712 *ice, unsigned int val);
	unsigned int (*get_register)(struct snd_ice1712 *ice);
	const char * const texts[2];
};

enum {
	IN12_SEL = 0,
	IN34_SEL,
	AIN34_SEL,
	COAX_OUT,
	IN12_MON12,
	IN12_MON34,
	IN34_MON12,
	IN34_MON34,
	OUT12_MON34,
	OUT34_MON12,
};

static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",
	"Word Clock 256xFS"};

/* chip address on I2C bus */
#define AK4113_ADDR		0x26	/* S/PDIF receiver */

/* chip address on SPI bus */
#define AK4620_ADDR		0x02	/* ADC/DAC */


/*
 * GPIO pins
 */

/* GPIO0 - O - DATA0, def. 0 */
#define GPIO_D0			(1<<0)
/* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
#define GPIO_D1_JACKDTC0	(1<<1)
/* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
#define GPIO_D2_JACKDTC1	(1<<2)
/* GPIO3 - I/O - DATA3, def. 1 */
#define GPIO_D3			(1<<3)
/* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
#define GPIO_D4_SPI_CDTO	(1<<4)
/* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
#define GPIO_D5_SPI_CCLK	(1<<5)
/* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */
#define GPIO_D6_CD		(1<<6)
/* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */
#define GPIO_D7_DD		(1<<7)
/* GPIO8 - O - CPLD Chip Select, def. 1 */
#define GPIO_CPLD_CSN		(1<<8)
/* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */
#define GPIO_CPLD_RW		(1<<9)
/* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */
#define GPIO_SPI_CSN0		(1<<10)
/* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */
#define GPIO_SPI_CSN1		(1<<11)
/* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1,
 * init 0 */
#define GPIO_EX_GPIOE		(1<<12)
/* GPIO13 - O - Ex. Register0 Chip Select for System Control Register,
 * def. 1 */
#define GPIO_SCR		(1<<13)
/* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register,
 * def. 1 */
#define GPIO_MCR		(1<<14)

#define GPIO_SPI_ALL		(GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\
		GPIO_SPI_CSN0 | GPIO_SPI_CSN1)

#define GPIO_DATA_MASK		(GPIO_D0 | GPIO_D1_JACKDTC0 | \
		GPIO_D2_JACKDTC1 | GPIO_D3 | \
		GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
		GPIO_D6_CD | GPIO_D7_DD)

/* System Control Register GPIO_SCR data bits */
/* Mic/Line select relay (0:line, 1:mic) */
#define SCR_RELAY		GPIO_D0
/* Phantom power drive control (0:5V, 1:48V) */
#define SCR_PHP_V		GPIO_D1_JACKDTC0
/* H/W mute control (0:Normal, 1:Mute) */
#define SCR_MUTE		GPIO_D2_JACKDTC1

Annotation

Implementation Notes