sound/soc/amd/include/acp_2_2_sh_mask.h
Source file repositories/reference/linux-study-clean/sound/soc/amd/include/acp_2_2_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
sound/soc/amd/include/acp_2_2_sh_mask.h- Extension
.h- Size
- 129656 bytes
- Lines
- 2277
- Domain
- Driver Families
- Bucket
- sound/soc
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ACP_2_2_SH_MASK_H
#define ACP_2_2_SH_MASK_H
#define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_1__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_1__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_1__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_1__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_1__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_1__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_1__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_1__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_1__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_1__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_2__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_2__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_2__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_2__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_2__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_2__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_2__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_2__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_2__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_2__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_3__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_3__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_3__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_3__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_3__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_3__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_3__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_3__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_3__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_3__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_4__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_4__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_4__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_4__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_4__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_4__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_4__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_4__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_4__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_4__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_5__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_5__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_5__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_5__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_5__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_5__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_5__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_5__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_5__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_5__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_6__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_6__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_6__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_6__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_6__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_6__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_6__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_6__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_6__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_6__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_7__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_7__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_7__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_7__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_7__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_7__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_7__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_7__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_7__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_7__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_8__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_8__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_8__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_8__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_8__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_8__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_8__Circular_DMA_En_MASK 0x8Annotation
- Atlas domain: Driver Families / sound/soc.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.