sound/soc/amd/renoir/rn_chip_offset_byte.h

Source file repositories/reference/linux-study-clean/sound/soc/amd/renoir/rn_chip_offset_byte.h

File Facts

System: Linux kernel
Corpus path: sound/soc/amd/renoir/rn_chip_offset_byte.h
Extension: .h
Size: 20408 bytes
Lines: 350
Domain: Driver Families
Bucket: sound/soc
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _rn_OFFSET_HEADER
#define _rn_OFFSET_HEADER
// Registers from ACP_DMA block

#define ACP_DMA_CNTL_0                                0x1240000
#define ACP_DMA_CNTL_1                                0x1240004
#define ACP_DMA_CNTL_2                                0x1240008
#define ACP_DMA_CNTL_3                                0x124000C
#define ACP_DMA_CNTL_4                                0x1240010
#define ACP_DMA_CNTL_5                                0x1240014
#define ACP_DMA_CNTL_6                                0x1240018
#define ACP_DMA_CNTL_7                                0x124001C
#define ACP_DMA_DSCR_STRT_IDX_0                       0x1240020
#define ACP_DMA_DSCR_STRT_IDX_1                       0x1240024
#define ACP_DMA_DSCR_STRT_IDX_2                       0x1240028
#define ACP_DMA_DSCR_STRT_IDX_3                       0x124002C
#define ACP_DMA_DSCR_STRT_IDX_4                       0x1240030
#define ACP_DMA_DSCR_STRT_IDX_5                       0x1240034
#define ACP_DMA_DSCR_STRT_IDX_6                       0x1240038
#define ACP_DMA_DSCR_STRT_IDX_7                       0x124003C
#define ACP_DMA_DSCR_CNT_0                            0x1240040
#define ACP_DMA_DSCR_CNT_1                            0x1240044
#define ACP_DMA_DSCR_CNT_2                            0x1240048
#define ACP_DMA_DSCR_CNT_3                            0x124004C
#define ACP_DMA_DSCR_CNT_4                            0x1240050
#define ACP_DMA_DSCR_CNT_5                            0x1240054
#define ACP_DMA_DSCR_CNT_6                            0x1240058
#define ACP_DMA_DSCR_CNT_7                            0x124005C
#define ACP_DMA_PRIO_0                                0x1240060
#define ACP_DMA_PRIO_1                                0x1240064
#define ACP_DMA_PRIO_2                                0x1240068
#define ACP_DMA_PRIO_3                                0x124006C
#define ACP_DMA_PRIO_4                                0x1240070
#define ACP_DMA_PRIO_5                                0x1240074
#define ACP_DMA_PRIO_6                                0x1240078
#define ACP_DMA_PRIO_7                                0x124007C
#define ACP_DMA_CUR_DSCR_0                            0x1240080
#define ACP_DMA_CUR_DSCR_1                            0x1240084
#define ACP_DMA_CUR_DSCR_2                            0x1240088
#define ACP_DMA_CUR_DSCR_3                            0x124008C
#define ACP_DMA_CUR_DSCR_4                            0x1240090
#define ACP_DMA_CUR_DSCR_5                            0x1240094
#define ACP_DMA_CUR_DSCR_6                            0x1240098
#define ACP_DMA_CUR_DSCR_7                            0x124009C
#define ACP_DMA_CUR_TRANS_CNT_0                       0x12400A0
#define ACP_DMA_CUR_TRANS_CNT_1                       0x12400A4
#define ACP_DMA_CUR_TRANS_CNT_2                       0x12400A8
#define ACP_DMA_CUR_TRANS_CNT_3                       0x12400AC
#define ACP_DMA_CUR_TRANS_CNT_4                       0x12400B0
#define ACP_DMA_CUR_TRANS_CNT_5                       0x12400B4
#define ACP_DMA_CUR_TRANS_CNT_6                       0x12400B8
#define ACP_DMA_CUR_TRANS_CNT_7                       0x12400BC
#define ACP_DMA_ERR_STS_0                             0x12400C0
#define ACP_DMA_ERR_STS_1                             0x12400C4
#define ACP_DMA_ERR_STS_2                             0x12400C8
#define ACP_DMA_ERR_STS_3                             0x12400CC
#define ACP_DMA_ERR_STS_4                             0x12400D0
#define ACP_DMA_ERR_STS_5                             0x12400D4
#define ACP_DMA_ERR_STS_6                             0x12400D8
#define ACP_DMA_ERR_STS_7                             0x12400DC
#define ACP_DMA_DESC_BASE_ADDR                        0x12400E0
#define ACP_DMA_DESC_MAX_NUM_DSCR                     0x12400E4
#define ACP_DMA_CH_STS                                0x12400E8
#define ACP_DMA_CH_GROUP                              0x12400EC
#define ACP_DMA_CH_RST_STS                            0x12400F0

// Registers from ACP_AXI2AXIATU block

#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1                0x1240C00
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1                0x1240C04
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2                0x1240C08
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2                0x1240C0C
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3                0x1240C10
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3                0x1240C14
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4                0x1240C18
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4                0x1240C1C
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5                0x1240C20
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5                0x1240C24
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6                0x1240C28
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6                0x1240C2C
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7                0x1240C30
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7                0x1240C34
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8                0x1240C38
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8                0x1240C3C
#define ACPAXI2AXI_ATU_CTRL                           0x1240C40

// Registers from ACP_CLKRST block

#define ACP_SOFT_RESET                                0x1241000
#define ACP_CONTROL                                   0x1241004

Annotation

Atlas domain: Driver Families / sound/soc.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.