sound/soc/codecs/cs35l33.h

Source file repositories/reference/linux-study-clean/sound/soc/codecs/cs35l33.h

File Facts

System
Linux kernel
Corpus path
sound/soc/codecs/cs35l33.h
Extension
.h
Size
7941 bytes
Lines
218
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __CS35L33_H__
#define __CS35L33_H__

#define CS35L33_CHIP_ID		0x00035A33
#define CS35L33_DEVID_AB	0x01	/* Device ID A & B [RO] */
#define CS35L33_DEVID_CD	0x02	/* Device ID C & D [RO] */
#define CS35L33_DEVID_E		0x03	/* Device ID E [RO] */
#define CS35L33_FAB_ID		0x04	/* Fab ID [RO] */
#define CS35L33_REV_ID		0x05	/* Revision ID [RO] */
#define CS35L33_PWRCTL1		0x06	/* Power Ctl 1 */
#define CS35L33_PWRCTL2		0x07	/* Power Ctl 2 */
#define CS35L33_CLK_CTL		0x08	/* Clock Ctl */
#define CS35L33_BST_PEAK_CTL	0x09	/* Max Current for Boost */
#define CS35L33_PROTECT_CTL	0x0A	/* Amp Protection Parameters */
#define CS35L33_BST_CTL1	0x0B	/* Boost Converter CTL1 */
#define CS35L33_BST_CTL2	0x0C	/* Boost Converter CTL2 */
#define CS35L33_ADSP_CTL	0x0D	/* Serial Port Control */
#define CS35L33_ADC_CTL		0x0E	/* ADC Control */
#define CS35L33_DAC_CTL		0x0F	/* DAC Control */
#define CS35L33_DIG_VOL_CTL	0x10	/* Digital Volume CTL */
#define CS35L33_CLASSD_CTL	0x11	/* Class D Amp CTL */
#define CS35L33_AMP_CTL		0x12	/* Amp Gain/Protecton Release CTL */
#define CS35L33_INT_MASK_1	0x13	/* Interrupt Mask 1 */
#define CS35L33_INT_MASK_2	0x14	/* Interrupt Mask 2 */
#define CS35L33_INT_STATUS_1	0x15	/* Interrupt Status 1 [RO] */
#define CS35L33_INT_STATUS_2	0x16	/* Interrupt Status 2 [RO] */
#define CS35L33_DIAG_LOCK	0x17	/* Diagnostic Mode Register Lock */
#define CS35L33_DIAG_CTRL_1	0x18	/* Diagnostic Mode Register Control */
#define CS35L33_DIAG_CTRL_2	0x19	/* Diagnostic Mode Register Control 2 */
#define CS35L33_HG_MEMLDO_CTL	0x23	/* H/G Memory/LDO CTL */
#define CS35L33_HG_REL_RATE	0x24	/* H/G Release Rate */
#define CS35L33_LDO_DEL		0x25	/* LDO Entry Delay/VPhg Control 1 */
#define CS35L33_HG_HEAD		0x29	/* H/G Headroom */
#define CS35L33_HG_EN		0x2A	/* H/G Enable/VPhg CNT2 */
#define CS35L33_TX_VMON		0x2D	/* TDM TX Control 1 (VMON) */
#define CS35L33_TX_IMON		0x2E	/* TDM TX Control 2 (IMON) */
#define CS35L33_TX_VPMON	0x2F	/* TDM TX Control 3 (VPMON) */
#define CS35L33_TX_VBSTMON	0x30	/* TDM TX Control 4 (VBSTMON) */
#define CS35L33_TX_FLAG		0x31	/* TDM TX Control 5 (FLAG) */
#define CS35L33_TX_EN1		0x32	/* TDM TX Enable 1 */
#define CS35L33_TX_EN2		0x33	/* TDM TX Enable 2 */
#define CS35L33_TX_EN3		0x34	/* TDM TX Enable 3 */
#define CS35L33_TX_EN4		0x35	/* TDM TX Enable 4 */
#define CS35L33_RX_AUD		0x36	/* TDM RX Control 1 */
#define CS35L33_RX_SPLY		0x37	/* TDM RX Control 2 */
#define CS35L33_RX_ALIVE	0x38	/* TDM RX Control 3 */
#define CS35L33_BST_CTL4	0x39	/* Boost Converter Control 4 */
#define CS35L33_HG_STATUS	0x3F	/* H/G Status */
#define CS35L33_MAX_REGISTER	0x59

#define CS35L33_MCLK_5644	5644800
#define CS35L33_MCLK_6144	6144000
#define CS35L33_MCLK_6		6000000
#define CS35L33_MCLK_11289	11289600
#define CS35L33_MCLK_12		12000000
#define CS35L33_MCLK_12288	12288000

/* CS35L33_PWRCTL1 */
#define CS35L33_PDN_AMP			(1 << 7)
#define CS35L33_PDN_BST			(1 << 2)
#define CS35L33_PDN_ALL			1

/* CS35L33_PWRCTL2 */
#define CS35L33_PDN_VMON_SHIFT		7
#define CS35L33_PDN_VMON		(1 << CS35L33_PDN_VMON_SHIFT)
#define CS35L33_PDN_IMON_SHIFT		6
#define CS35L33_PDN_IMON		(1 << CS35L33_PDN_IMON_SHIFT)
#define CS35L33_PDN_VPMON_SHIFT		5
#define CS35L33_PDN_VPMON		(1 << CS35L33_PDN_VPMON_SHIFT)
#define CS35L33_PDN_VBSTMON_SHIFT	4
#define CS35L33_PDN_VBSTMON		(1 << CS35L33_PDN_VBSTMON_SHIFT)
#define CS35L33_SDOUT_3ST_I2S_SHIFT	3
#define CS35L33_SDOUT_3ST_I2S		(1 << CS35L33_SDOUT_3ST_I2S_SHIFT)
#define CS35L33_PDN_SDIN_SHIFT		2
#define CS35L33_PDN_SDIN		(1 << CS35L33_PDN_SDIN_SHIFT)
#define CS35L33_PDN_TDM_SHIFT		1
#define CS35L33_PDN_TDM			(1 << CS35L33_PDN_TDM_SHIFT)

/* CS35L33_CLK_CTL */
#define CS35L33_MCLKDIS			(1 << 7)
#define CS35L33_MCLKDIV2		(1 << 6)
#define CS35L33_SDOUT_3ST_TDM		(1 << 5)
#define CS35L33_INT_FS_RATE		(1 << 4)
#define CS35L33_ADSP_FS			0xF

/* CS35L33_PROTECT_CTL */
#define CS35L33_ALIVE_WD_DIS		(3 << 2)

/* CS35L33_BST_CTL1 */
#define CS35L33_BST_CTL_SRC		(1 << 6)

Annotation

Implementation Notes