sound/soc/codecs/cs42l56.c

Source file repositories/reference/linux-study-clean/sound/soc/codecs/cs42l56.c

File Facts

System
Linux kernel
Corpus path
sound/soc/codecs/cs42l56.c
Extension
.c
Size
41904 bytes
Lines
1376
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cs42l56_platform_data {
	/* GPIO for Reset */
	struct gpio_desc *gpio_nreset;

	/* MICBIAS Level. Check datasheet Pg48 */
	unsigned int micbias_lvl;

	/* Analog Input 1A Reference 0=Single 1=Pseudo-Differential */
	unsigned int ain1a_ref_cfg;

	/* Analog Input 2A Reference 0=Single 1=Pseudo-Differential */
	unsigned int ain2a_ref_cfg;

	/* Analog Input 1B Reference 0=Single 1=Pseudo-Differential */
	unsigned int ain1b_ref_cfg;

	/* Analog Input 2B Reference 0=Single 1=Pseudo-Differential */
	unsigned int ain2b_ref_cfg;

	/* Charge Pump Freq. Check datasheet Pg62 */
	unsigned int chgfreq;

	/* HighPass Filter Right Channel Corner Frequency */
	unsigned int hpfb_freq;

	/* HighPass Filter Left Channel Corner Frequency */
	unsigned int hpfa_freq;

	/* Adaptive Power Control for LO/HP */
	unsigned int adaptive_pwr;
};

static const char *const cs42l56_supply_names[CS42L56_NUM_SUPPLIES] = {
	"VA",
	"VCP",
	"VLDO",
};

struct  cs42l56_private {
	struct regmap *regmap;
	struct snd_soc_component *component;
	struct device *dev;
	struct cs42l56_platform_data pdata;
	struct regulator_bulk_data supplies[CS42L56_NUM_SUPPLIES];
	u32 mclk;
	u8 mclk_prediv;
	u8 mclk_div2;
	u8 mclk_ratio;
	u8 iface;
	u8 iface_fmt;
	u8 iface_inv;
#if IS_ENABLED(CONFIG_INPUT)
	struct input_dev *beep;
	struct work_struct beep_work;
	int beep_rate;
#endif
};

static const struct reg_default cs42l56_reg_defaults[] = {
	{ 3, 0x7f },	/* r03	- Power Ctl 1 */
	{ 4, 0xff },	/* r04	- Power Ctl 2 */
	{ 5, 0x00 },	/* ro5	- Clocking Ctl 1 */
	{ 6, 0x0b },	/* r06	- Clocking Ctl 2 */
	{ 7, 0x00 },	/* r07	- Serial Format */
	{ 8, 0x05 },	/* r08	- Class H Ctl */
	{ 9, 0x0c },	/* r09	- Misc Ctl */
	{ 10, 0x80 },	/* r0a	- INT Status */
	{ 11, 0x00 },	/* r0b	- Playback Ctl */
	{ 12, 0x0c },	/* r0c	- DSP Mute Ctl */
	{ 13, 0x00 },	/* r0d	- ADCA Mixer Volume */
	{ 14, 0x00 },	/* r0e	- ADCB Mixer Volume */
	{ 15, 0x00 },	/* r0f	- PCMA Mixer Volume */
	{ 16, 0x00 },	/* r10	- PCMB Mixer Volume */
	{ 17, 0x00 },	/* r11	- Analog Input Advisory Volume */
	{ 18, 0x00 },	/* r12	- Digital Input Advisory Volume */
	{ 19, 0x00 },	/* r13	- Master A Volume */
	{ 20, 0x00 },	/* r14	- Master B Volume */
	{ 21, 0x00 },	/* r15	- Beep Freq / On Time */
	{ 22, 0x00 },	/* r16	- Beep Volume / Off Time */
	{ 23, 0x00 },	/* r17	- Beep Tone Ctl */
	{ 24, 0x88 },	/* r18	- Tone Ctl */
	{ 25, 0x00 },	/* r19	- Channel Mixer & Swap */
	{ 26, 0x00 },	/* r1a	- AIN Ref Config / ADC Mux */
	{ 27, 0xa0 },	/* r1b	- High-Pass Filter Ctl */
	{ 28, 0x00 },	/* r1c	- Misc ADC Ctl */
	{ 29, 0x00 },	/* r1d	- Gain & Bias Ctl */
	{ 30, 0x00 },	/* r1e	- PGAA Mux & Volume */
	{ 31, 0x00 },	/* r1f	- PGAB Mux & Volume */
	{ 32, 0x00 },	/* r20	- ADCA Attenuator */
	{ 33, 0x00 },	/* r21	- ADCB Attenuator */

Annotation

Implementation Notes