sound/soc/codecs/cs42l84.h

Source file repositories/reference/linux-study-clean/sound/soc/codecs/cs42l84.h

File Facts

System
Linux kernel
Corpus path
sound/soc/codecs/cs42l84.h
Extension
.h
Size
7298 bytes
Lines
211
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __CS42L84_H__
#define __CS42L84_H__

#include <linux/bits.h>

#define CS42L84_CHIP_ID				0x42a84

#define CS42L84_DEVID				0x0000
#define CS42L84_REVID				0x73fe
#define CS42L84_FRZ_CTL				0x0006
#define CS42L84_FRZ_CTL_ENGAGE			BIT(0)

#define CS42L84_TSRS_PLUG_INT_STATUS		0x0400
#define CS42L84_TSRS_PLUG_INT_MASK		0x0418
#define CS42L84_RS_PLUG_SHIFT			0
#define CS42L84_RS_PLUG				BIT(0)
#define CS42L84_RS_UNPLUG			BIT(1)
#define CS42L84_TS_PLUG_SHIFT			2
#define CS42L84_TS_PLUG				BIT(2)
#define CS42L84_TS_UNPLUG			BIT(3)
#define CS42L84_TSRS_PLUG_VAL_MASK		GENMASK(3, 0)
#define CS42L84_PLL_LOCK_STATUS			0x040e // probably bit 0x10
#define CS42L84_PLL_LOCK_STATUS_LOCKED		BIT(4)
#define CS42L84_PLL_LOCK_STATUS_ERROR		BIT(5)

#define CS42L84_PLUG				3
#define CS42L84_UNPLUG				0
#define CS42L84_TRANS				1

#define CS42L84_CCM_CTL1			0x0600
#define CS42L84_CCM_CTL1_MCLK_SRC		GENMASK(1, 0)
#define CS42L84_CCM_CTL1_MCLK_SRC_RCO		0
#define CS42L84_CCM_CTL1_MCLK_SRC_MCLK		1
#define CS42L84_CCM_CTL1_MCLK_SRC_BCLK		2
#define CS42L84_CCM_CTL1_MCLK_SRC_PLL		3
#define CS42L84_CCM_CTL1_MCLK_FREQ		GENMASK(3, 2)
#define CS42L84_CCM_CTL1_MCLK_F_12MHZ		0b00
#define CS42L84_CCM_CTL1_MCLK_F_24MHZ		0b01
#define CS42L84_CCM_CTL1_MCLK_F_12_288KHZ	0b10
#define CS42L84_CCM_CTL1_MCLK_F_24_576KHZ	0b11
#define CS42L84_CCM_CTL1_RCO \
	(FIELD_PREP(CS42L84_CCM_CTL1_MCLK_SRC, CS42L84_CCM_CTL1_MCLK_SRC_RCO) \
	| FIELD_PREP(CS42L84_CCM_CTL1_MCLK_FREQ, CS42L84_CCM_CTL1_MCLK_F_12MHZ))

#define CS42L84_CCM_SAMP_RATE			0x0601
#define CS42L84_CCM_SAMP_RATE_RATE_48KHZ	4
#define CS42L84_CCM_SAMP_RATE_RATE_96KHZ	5
#define CS42L84_CCM_SAMP_RATE_RATE_192KHZ	6
#define CS42L84_CCM_SAMP_RATE_RATE_44K1HZ	12
#define CS42L84_CCM_SAMP_RATE_RATE_88K2HZ	13
#define CS42L84_CCM_SAMP_RATE_RATE_176K4HZ	14
#define CS42L84_CCM_CTL3			0x0602
#define CS42L84_CCM_CTL3_REFCLK_DIV		GENMASK(2, 1)
#define CS42L84_CCM_CTL4			0x0603
#define CS42L84_CCM_CTL4_REFCLK_EN		BIT(0)

#define CS42L84_CCM_ASP_CLK_CTRL		0x0608

#define CS42L84_PLL_CTL1			0x0800
#define CS42L84_PLL_CTL1_EN			BIT(0)
#define CS42L84_PLL_CTL1_MODE			GENMASK(2, 1)
#define CS42L84_PLL_DIV_FRAC0			0x0804
#define CS42L84_PLL_DIV_FRAC1			0x0805
#define CS42L84_PLL_DIV_FRAC2			0x0806
#define CS42L84_PLL_DIV_INT			0x0807
#define CS42L84_PLL_DIVOUT			0x0808

#define CS42L84_RING_SENSE_CTL			0x1282
#define CS42L84_RING_SENSE_CTL_INV		BIT(7)
#define CS42L84_RING_SENSE_CTL_UNK1		BIT(6)
#define CS42L84_RING_SENSE_CTL_FALLTIME		GENMASK(5, 3)
#define CS42L84_RING_SENSE_CTL_RISETIME		GENMASK(2, 0)
#define CS42L84_TIP_SENSE_CTL			0x1283
#define CS42L84_TIP_SENSE_CTL_INV		BIT(7)
#define CS42L84_TIP_SENSE_CTL_FALLTIME		GENMASK(5, 3)
#define CS42L84_TIP_SENSE_CTL_RISETIME		GENMASK(2, 0)

#define CS42L84_TSRS_PLUG_STATUS		0x1288

#define CS42L84_TIP_SENSE_CTL2			0x1473
#define CS42L84_TIP_SENSE_CTL2_MODE		GENMASK(7, 6)
#define CS42L84_TIP_SENSE_CTL2_MODE_DISABLED	0b00
#define CS42L84_TIP_SENSE_CTL2_MODE_DIG_INPUT	0b01
#define CS42L84_TIP_SENSE_CTL2_MODE_SHORT_DET	0b11
#define CS42L84_TIP_SENSE_CTL2_INV		BIT(5)

#define CS42L84_MISC_DET_CTL			0x1474
#define CS42L84_MISC_DET_CTL_DETECT_MODE	GENMASK(4, 3)
#define CS42L84_MISC_DET_CTL_HSBIAS_CTL		GENMASK(2, 1)
#define CS42L84_MISC_DET_CTL_PDN_MIC_LVL_DET	BIT(0)

Annotation

Implementation Notes