sound/soc/codecs/lm49453.h

Source file repositories/reference/linux-study-clean/sound/soc/codecs/lm49453.h

File Facts

System
Linux kernel
Corpus path
sound/soc/codecs/lm49453.h
Extension
.h
Size
13711 bytes
Lines
377
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _LM49453_H
#define _LM49453_H

#include <linux/bitops.h>

/* LM49453_P0 register space for page0 */
#define LM49453_P0_PMC_SETUP_REG			0x00
#define LM49453_P0_PLL_CLK_SEL1_REG			0x01
#define LM49453_P0_PLL_CLK_SEL2_REG			0x02
#define LM49453_P0_PMC_CLK_DIV_REG			0x03
#define LM49453_P0_HSDET_CLK_DIV_REG			0x04
#define LM49453_P0_DMIC_CLK_DIV_REG			0x05
#define LM49453_P0_ADC_CLK_DIV_REG			0x06
#define LM49453_P0_DAC_OT_CLK_DIV_REG			0x07
#define LM49453_P0_PLL_HF_M_REG				0x08
#define LM49453_P0_PLL_LF_M_REG				0x09
#define LM49453_P0_PLL_NL_REG				0x0A
#define LM49453_P0_PLL_N_MODL_REG			0x0B
#define LM49453_P0_PLL_N_MODH_REG			0x0C
#define LM49453_P0_PLL_P1_REG				0x0D
#define LM49453_P0_PLL_P2_REG				0x0E
#define LM49453_P0_FLL_REF_FREQL_REG			0x0F
#define LM49453_P0_FLL_REF_FREQH_REG			0x10
#define LM49453_P0_VCO_TARGETLL_REG			0x11
#define LM49453_P0_VCO_TARGETLH_REG			0x12
#define LM49453_P0_VCO_TARGETHL_REG			0x13
#define LM49453_P0_VCO_TARGETHH_REG			0x14
#define LM49453_P0_PLL_CONFIG_REG			0x15
#define LM49453_P0_DAC_CLK_SEL_REG			0x16
#define LM49453_P0_DAC_HP_CLK_DIV_REG			0x17

/* Analog Mixer Input Stages */
#define LM49453_P0_MICL_REG				0x20
#define LM49453_P0_MICR_REG				0x21
#define LM49453_P0_EP_REG				0x24
#define LM49453_P0_DIS_PKVL_FB_REG			0x25

/* Analog Mixer Output Stages */
#define LM49453_P0_ANALOG_MIXER_ADC_REG			0x2E

/*ADC or DAC */
#define LM49453_P0_ADC_DSP_REG				0x30
#define LM49453_P0_DAC_DSP_REG				0x31

/* EFFECTS ENABLES */
#define LM49453_P0_ADC_FX_ENABLES_REG			0x33

/* GPIO */
#define LM49453_P0_GPIO1_REG				0x38
#define LM49453_P0_GPIO2_REG				0x39
#define LM49453_P0_GPIO3_REG				0x3A
#define LM49453_P0_HAP_CTL_REG				0x3B
#define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG		0x3C
#define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG		0x3D
#define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG		0x3E
#define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG		0x3F

/* DIGITAL MIXER */
#define LM49453_P0_DMIX_CLK_SEL_REG			0x40
#define LM49453_P0_PORT1_RX_LVL1_REG			0x41
#define LM49453_P0_PORT1_RX_LVL2_REG			0x42
#define LM49453_P0_PORT2_RX_LVL_REG			0x43
#define LM49453_P0_PORT1_TX1_REG			0x44
#define LM49453_P0_PORT1_TX2_REG			0x45
#define LM49453_P0_PORT1_TX3_REG			0x46
#define LM49453_P0_PORT1_TX4_REG			0x47
#define LM49453_P0_PORT1_TX5_REG			0x48
#define LM49453_P0_PORT1_TX6_REG			0x49
#define LM49453_P0_PORT1_TX7_REG			0x4A
#define LM49453_P0_PORT1_TX8_REG			0x4B
#define LM49453_P0_PORT2_TX1_REG			0x4C
#define LM49453_P0_PORT2_TX2_REG			0x4D
#define LM49453_P0_STN_SEL_REG				0x4F
#define LM49453_P0_DACHPL1_REG				0x50
#define LM49453_P0_DACHPL2_REG				0x51
#define LM49453_P0_DACHPR1_REG				0x52
#define LM49453_P0_DACHPR2_REG				0x53
#define LM49453_P0_DACLOL1_REG				0x54
#define LM49453_P0_DACLOL2_REG				0x55
#define LM49453_P0_DACLOR1_REG				0x56
#define LM49453_P0_DACLOR2_REG				0x57
#define LM49453_P0_DACLSL1_REG				0x58
#define LM49453_P0_DACLSL2_REG				0x59
#define LM49453_P0_DACLSR1_REG				0x5A
#define LM49453_P0_DACLSR2_REG				0x5B
#define LM49453_P0_DACHAL1_REG				0x5C
#define LM49453_P0_DACHAL2_REG				0x5D
#define LM49453_P0_DACHAR1_REG				0x5E
#define LM49453_P0_DACHAR2_REG				0x5F

Annotation

Implementation Notes