sound/soc/codecs/max98088.h

Source file repositories/reference/linux-study-clean/sound/soc/codecs/max98088.h

File Facts

System: Linux kernel
Corpus path: sound/soc/codecs/max98088.h
Extension: .h
Size: 8385 bytes
Lines: 204
Domain: Driver Families
Bucket: sound/soc
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _MAX98088_H
#define _MAX98088_H

/*
 * MAX98088 Registers Definition
 */
#define M98088_REG_00_IRQ_STATUS            0x00
#define M98088_REG_01_MIC_STATUS            0x01
#define M98088_REG_02_JACK_STATUS           0x02
#define M98088_REG_03_BATTERY_VOLTAGE       0x03
#define M98088_REG_0F_IRQ_ENABLE            0x0F
#define M98088_REG_10_SYS_CLK               0x10
#define M98088_REG_11_DAI1_CLKMODE          0x11
#define M98088_REG_12_DAI1_CLKCFG_HI        0x12
#define M98088_REG_13_DAI1_CLKCFG_LO        0x13
#define M98088_REG_14_DAI1_FORMAT           0x14
#define M98088_REG_15_DAI1_CLOCK            0x15
#define M98088_REG_16_DAI1_IOCFG            0x16
#define M98088_REG_17_DAI1_TDM              0x17
#define M98088_REG_18_DAI1_FILTERS          0x18
#define M98088_REG_19_DAI2_CLKMODE          0x19
#define M98088_REG_1A_DAI2_CLKCFG_HI        0x1A
#define M98088_REG_1B_DAI2_CLKCFG_LO        0x1B
#define M98088_REG_1C_DAI2_FORMAT           0x1C
#define M98088_REG_1D_DAI2_CLOCK            0x1D
#define M98088_REG_1E_DAI2_IOCFG            0x1E
#define M98088_REG_1F_DAI2_TDM              0x1F
#define M98088_REG_20_DAI2_FILTERS          0x20
#define M98088_REG_21_SRC                   0x21
#define M98088_REG_22_MIX_DAC               0x22
#define M98088_REG_23_MIX_ADC_LEFT          0x23
#define M98088_REG_24_MIX_ADC_RIGHT         0x24
#define M98088_REG_25_MIX_HP_LEFT           0x25
#define M98088_REG_26_MIX_HP_RIGHT          0x26
#define M98088_REG_27_MIX_HP_CNTL           0x27
#define M98088_REG_28_MIX_REC_LEFT          0x28
#define M98088_REG_29_MIX_REC_RIGHT         0x29
#define M98088_REG_2A_MIC_REC_CNTL          0x2A
#define M98088_REG_2B_MIX_SPK_LEFT          0x2B
#define M98088_REG_2C_MIX_SPK_RIGHT         0x2C
#define M98088_REG_2D_MIX_SPK_CNTL          0x2D
#define M98088_REG_2E_LVL_SIDETONE          0x2E
#define M98088_REG_2F_LVL_DAI1_PLAY         0x2F
#define M98088_REG_30_LVL_DAI1_PLAY_EQ      0x30
#define M98088_REG_31_LVL_DAI2_PLAY         0x31
#define M98088_REG_32_LVL_DAI2_PLAY_EQ      0x32
#define M98088_REG_33_LVL_ADC_L             0x33
#define M98088_REG_34_LVL_ADC_R             0x34
#define M98088_REG_35_LVL_MIC1              0x35
#define M98088_REG_36_LVL_MIC2              0x36
#define M98088_REG_37_LVL_INA               0x37
#define M98088_REG_38_LVL_INB               0x38
#define M98088_REG_39_LVL_HP_L              0x39
#define M98088_REG_3A_LVL_HP_R              0x3A
#define M98088_REG_3B_LVL_REC_L             0x3B
#define M98088_REG_3C_LVL_REC_R             0x3C
#define M98088_REG_3D_LVL_SPK_L             0x3D
#define M98088_REG_3E_LVL_SPK_R             0x3E
#define M98088_REG_3F_MICAGC_CFG            0x3F
#define M98088_REG_40_MICAGC_THRESH         0x40
#define M98088_REG_41_SPKDHP                0x41
#define M98088_REG_42_SPKDHP_THRESH         0x42
#define M98088_REG_43_SPKALC_COMP           0x43
#define M98088_REG_44_PWRLMT_CFG            0x44
#define M98088_REG_45_PWRLMT_TIME           0x45
#define M98088_REG_46_THDLMT_CFG            0x46
#define M98088_REG_47_CFG_AUDIO_IN          0x47
#define M98088_REG_48_CFG_MIC               0x48
#define M98088_REG_49_CFG_LEVEL             0x49
#define M98088_REG_4A_CFG_BYPASS            0x4A
#define M98088_REG_4B_CFG_JACKDET           0x4B
#define M98088_REG_4C_PWR_EN_IN             0x4C
#define M98088_REG_4D_PWR_EN_OUT            0x4D
#define M98088_REG_4E_BIAS_CNTL             0x4E
#define M98088_REG_4F_DAC_BIAS1             0x4F
#define M98088_REG_50_DAC_BIAS2             0x50
#define M98088_REG_51_PWR_SYS               0x51
#define M98088_REG_52_DAI1_EQ_BASE          0x52
#define M98088_REG_84_DAI2_EQ_BASE          0x84
#define M98088_REG_B6_DAI1_BIQUAD_BASE      0xB6
#define M98088_REG_C0_DAI2_BIQUAD_BASE      0xC0
#define M98088_REG_FF_REV_ID                0xFF

#define M98088_REG_CNT                      (0xFF+1)

/* MAX98088 Registers Bit Fields */

/* M98088_REG_11_DAI1_CLKMODE, M98088_REG_19_DAI2_CLKMODE */
       #define M98088_CLKMODE_MASK             0xFF

Annotation

Atlas domain: Driver Families / sound/soc.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.