sound/soc/codecs/tac5xx2.h

Source file repositories/reference/linux-study-clean/sound/soc/codecs/tac5xx2.h

File Facts

System: Linux kernel
Corpus path: sound/soc/codecs/tac5xx2.h
Extension: .h
Size: 9481 bytes
Lines: 260
Domain: Driver Families
Bucket: sound/soc
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __RGL_TAC5XX2_H__
#define __RGL_TAC5XX2_H__

/* for soundwire */
#define TAC_REG_SDW(book, page, reg) (((book) * 256 * 128) + \
				      0x3000000 + ((page) * 128) + (reg))

/* page 0 registers */
#define TAC_SW_RESET		TAC_REG_SDW(0, 0, 1)
#define TAC_SLEEP_MODEZ		TAC_REG_SDW(0, 0, 2)
#define TAC_FEATURE_PDZ		TAC_REG_SDW(0, 0, 3)
#define TAC_TX_CH_EN		TAC_REG_SDW(0, 0, 4)
#define TAC_RX_CH_PD		TAC_REG_SDW(0, 0, 5)
#define TAC_SHDNZ_CFG		TAC_REG_SDW(0, 0, 6)
#define TAC_MISC_CFG0		TAC_REG_SDW(0, 0, 7)
#define TAC_MISC_CFG1		TAC_REG_SDW(0, 0, 8)
#define TAC_GPIO1_CFG0		TAC_REG_SDW(0, 0, 9)
#define TAC_GPIO2_CFG0		TAC_REG_SDW(0, 0, 10)
#define TAC_GPIO3_CFG0		TAC_REG_SDW(0, 0, 11)
#define TAC_GPIO4_CFG0		TAC_REG_SDW(0, 0, 12)
#define TAC_GPIO5_CFG0		TAC_REG_SDW(0, 0, 13)
#define TAC_GPIO6_CFG0		TAC_REG_SDW(0, 0, 14)
#define TAC_INTF_CFG1		TAC_REG_SDW(0, 0, 15)
#define TAC_INTF_CFG5		TAC_REG_SDW(0, 0, 16)
#define TAC_PASI_BCLK_CFG0	TAC_REG_SDW(0, 0, 17)
#define TAC_PASI_FSYNC_CFG0	TAC_REG_SDW(0, 0, 18)
#define TAC_PASI_DIN1_CFG0	TAC_REG_SDW(0, 0, 19)
#define TAC_PASI_DIN2_CFG0	TAC_REG_SDW(0, 0, 20)
#define TAC_PDM_DIN1_CFG0	TAC_REG_SDW(0, 0, 21)
#define TAC_PDM_DIN2_CFG0	TAC_REG_SDW(0, 0, 22)
#define TAC_MCLK_SEL		TAC_REG_SDW(0, 0, 23)
#define TAC_I2C2_CFG0		TAC_REG_SDW(0, 0, 24)
#define TAC_SDW_IO_CFG0		TAC_REG_SDW(0, 0, 25)
#define TAC_SDW_CLK_CFG0	TAC_REG_SDW(0, 0, 26)
#define TAC_PASI_CFG0		TAC_REG_SDW(0, 0, 27)
#define TAC_PASI_CFG1		TAC_REG_SDW(0, 0, 28)
#define TAC_PASI_TX_CFG0	TAC_REG_SDW(0, 0, 29)
#define TAC_PASI_TX_CFG1	TAC_REG_SDW(0, 0, 30)
#define TAC_PASI_TX_CFG2	TAC_REG_SDW(0, 0, 31)
#define TAC_PASI_TX_CFG3	TAC_REG_SDW(0, 0, 32)
#define TAC_PASI_TX_CH1_CFG0	TAC_REG_SDW(0, 0, 33)
#define TAC_PASI_TX_CH2_CFG0	TAC_REG_SDW(0, 0, 34)
#define TAC_PASI_TX_CH3_CFG0	TAC_REG_SDW(0, 0, 35)
#define TAC_PASI_TX_CH4_CFG0	TAC_REG_SDW(0, 0, 36)
#define TAC_PASI_TX_CH5_CFG0	TAC_REG_SDW(0, 0, 37)
#define TAC_PASI_TX_CH6_CFG0	TAC_REG_SDW(0, 0, 38)
#define TAC_PASI_TX_CH7_CFG0	TAC_REG_SDW(0, 0, 39)
#define TAC_PASI_TX_CH8_CFG0	TAC_REG_SDW(0, 0, 40)
#define TAC_PASI_RX_CFG0	TAC_REG_SDW(0, 0, 41)
#define TAC_PASI_RX_CFG1	TAC_REG_SDW(0, 0, 42)
#define TAC_PASI_RX_CFG2	TAC_REG_SDW(0, 0, 43)
#define TAC_PASI_RX_CH1_CFG0	TAC_REG_SDW(0, 0, 44)
#define TAC_PASI_RX_CH2_CFG0	TAC_REG_SDW(0, 0, 45)
#define TAC_PASI_RX_CH3_CFG0	TAC_REG_SDW(0, 0, 46)
#define TAC_PASI_RX_CH4_CFG0	TAC_REG_SDW(0, 0, 47)
#define TAC_PASI_RX_CH5_CFG0	TAC_REG_SDW(0, 0, 48)
#define TAC_PASI_RX_CH6_CFG0	TAC_REG_SDW(0, 0, 49)
#define TAC_PASI_RX_CH7_CFG0	TAC_REG_SDW(0, 0, 50)
#define TAC_PASI_RX_CH8_CFG0	TAC_REG_SDW(0, 0, 51)
#define TAC_ADC_CH1_CFG0	TAC_REG_SDW(0, 0, 52)
#define TAC_ADC_DVOL_CFG0	TAC_REG_SDW(0, 0, 53)
#define TAC_ADC_CH1_FGAIN	TAC_REG_SDW(0, 0, 54)
#define TAC_ADC_CH1_CFG1	TAC_REG_SDW(0, 0, 55)
#define TAC_ADC_CH2_CFG0	TAC_REG_SDW(0, 0, 57)
#define TAC_ADC_DVOL_CFG1	TAC_REG_SDW(0, 0, 58)
#define TAC_ADC_CH2_FGAIN	TAC_REG_SDW(0, 0, 59)
#define TAC_ADC_CH2_CFG1	TAC_REG_SDW(0, 0, 60)
#define TAC_ADC_CFG1		TAC_REG_SDW(0, 0, 62)
#define TAC_PDM_CH1_DVOL	TAC_REG_SDW(0, 0, 63)
#define TAC_PDM_CH1_FGAIN	TAC_REG_SDW(0, 0, 64)
#define TAC_PDM_CH1_CFG0	TAC_REG_SDW(0, 0, 65)
#define TAC_PDM_CH2_DVOL	TAC_REG_SDW(0, 0, 67)
#define TAC_PDM_CH2_FGAIN	TAC_REG_SDW(0, 0, 68)
#define TAC_PDM_CH2_CFG2	TAC_REG_SDW(0, 0, 69)
#define TAC_PDM_CH3_DVOL	TAC_REG_SDW(0, 0, 71)
#define TAC_PDM_CH3_FGAIN	TAC_REG_SDW(0, 0, 72)
#define TAC_PDM_CH3_CFG0	TAC_REG_SDW(0, 0, 73)
#define TAC_PDM_CH4_DVOL	TAC_REG_SDW(0, 0, 75)
#define TAC_PDM_CH4_FGAIN	TAC_REG_SDW(0, 0, 76)
#define TAC_PDM_CH4_CFG0	TAC_REG_SDW(0, 0, 77)
#define TAC_MICBIAS_CFG0	TAC_REG_SDW(0, 0, 79)
#define TAC_MICPREAMP_CFG	TAC_REG_SDW(0, 0, 80)
#define TAC_MICBIAS_CFG1	TAC_REG_SDW(0, 0, 81)
#define TAC_CLASSD_CH1_DVOL	TAC_REG_SDW(0, 0, 82)
#define TAC_CLASSD_CH1_FGAIN	TAC_REG_SDW(0, 0, 83)
#define TAC_CLASSD_CH2_DVOL	TAC_REG_SDW(0, 0, 85)
#define TAC_CLASSD_CH2_FGAIN	TAC_REG_SDW(0, 0, 86)
#define TAC_GCHP_CH1_DVOL	TAC_REG_SDW(0, 0, 88)
#define TAC_GCHP_CH1_FGAIN	TAC_REG_SDW(0, 0, 89)
#define TAC_GCHP_CH2_DVOL	TAC_REG_SDW(0, 0, 91)

Annotation

Atlas domain: Driver Families / sound/soc.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.