sound/soc/codecs/wcd-clsh-v2.c

File Facts

System

Linux kernel

Corpus path

sound/soc/codecs/wcd-clsh-v2.c

Extension

.c

Size

28192 bytes

Lines

903

Domain

Driver Families

Bucket

sound/soc

Inferred role

Driver Families: exported/initcall integration point

Status

integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/slab.h
• sound/soc.h
• linux/kernel.h
• linux/delay.h
• wcd9335.h
• wcd-clsh-v2.h

Detected Declarations

• struct wcd_clsh_ctrl
• function wcd_enable_clsh_block
• function wcd_clsh_set_buck_mode
• function wcd_clsh_v3_set_buck_mode
• function wcd_clsh_set_flyback_mode
• function wcd_clsh_buck_ctrl
• function wcd_clsh_v3_buck_ctrl
• function wcd_clsh_flyback_ctrl
• function wcd_clsh_set_gain_path
• function wcd_clsh_v2_set_hph_mode
• function wcd_clsh_v3_set_hph_mode
• function wcd_clsh_set_hph_mode
• function wcd_clsh_set_flyback_current
• function wcd_clsh_set_buck_regulator_mode
• function wcd_clsh_v3_set_buck_regulator_mode
• function wcd_clsh_v3_set_flyback_mode
• function wcd_clsh_v3_force_iq_ctl
• function wcd_clsh_v3_flyback_ctrl
• function wcd_clsh_v3_set_flyback_current
• function wcd_clsh_v3_state_aux
• function wcd_clsh_state_lo
• function wcd_clsh_v3_state_hph_r
• function wcd_clsh_state_hph_r
• function wcd_clsh_v3_state_hph_l
• function wcd_clsh_state_hph_l
• function wcd_clsh_v3_state_ear
• function wcd_clsh_state_ear
• function _wcd_clsh_ctrl_set_state
• function wcd_clsh_is_state_valid
• function wcd_clsh_ctrl_set_state
• function wcd_clsh_ctrl_get_state
• function wcd_clsh_ctrl_free
• export wcd_clsh_set_hph_mode
• export wcd_clsh_ctrl_set_state
• export wcd_clsh_ctrl_get_state
• export wcd_clsh_ctrl_alloc
• export wcd_clsh_ctrl_free

Annotated Snippet

struct wcd_clsh_ctrl {
	int state;
	int mode;
	int flyback_users;
	int buck_users;
	int clsh_users;
	int codec_version;
	struct snd_soc_component *comp;
};

/* Class-H registers for codecs from and above WCD9335 */
#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0			WCD9335_REG(0xB, 0x42)
#define WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK		BIT(6)
#define WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE		BIT(6)
#define WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE		0
#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0			WCD9335_REG(0xB, 0x56)
#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0			WCD9335_REG(0xB, 0x6A)
#define WCD9XXX_A_CDC_CLSH_K1_MSB			WCD9335_REG(0xC, 0x08)
#define WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK		GENMASK(3, 0)
#define WCD9XXX_A_CDC_CLSH_K1_LSB			WCD9335_REG(0xC, 0x09)
#define WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK		GENMASK(7, 0)
#define WCD9XXX_A_ANA_RX_SUPPLIES			WCD9335_REG(0x6, 0x08)
#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK		BIT(1)
#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H		0
#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB		BIT(1)
#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK		BIT(2)
#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA		BIT(2)
#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT		0
#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK		BIT(3)
#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA		BIT(3)
#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT		0
#define WCD9XXX_A_ANA_RX_VNEG_EN_MASK			BIT(6)
#define WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT			6
#define WCD9XXX_A_ANA_RX_VNEG_ENABLE			BIT(6)
#define WCD9XXX_A_ANA_RX_VNEG_DISABLE			0
#define WCD9XXX_A_ANA_RX_VPOS_EN_MASK			BIT(7)
#define WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT			7
#define WCD9XXX_A_ANA_RX_VPOS_ENABLE			BIT(7)
#define WCD9XXX_A_ANA_RX_VPOS_DISABLE			0
#define WCD9XXX_A_ANA_HPH				WCD9335_REG(0x6, 0x09)
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK		GENMASK(3, 2)
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA		0x08
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP			0x04
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL		0x0
#define WCD9XXX_A_CDC_CLSH_CRC				WCD9335_REG(0xC, 0x01)
#define WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK		BIT(0)
#define WCD9XXX_A_CDC_CLSH_CRC_CLK_ENABLE		BIT(0)
#define WCD9XXX_A_CDC_CLSH_CRC_CLK_DISABLE		0
#define WCD9XXX_FLYBACK_EN				WCD9335_REG(0x6, 0xA4)
#define WCD9XXX_FLYBACK_EN_DELAY_SEL_MASK		GENMASK(6, 5)
#define WCD9XXX_FLYBACK_EN_DELAY_26P25_US		0x40
#define WCD9XXX_FLYBACK_EN_RESET_BY_EXT_MASK		BIT(4)
#define WCD9XXX_FLYBACK_EN_PWDN_WITHOUT_DELAY		BIT(4)
#define WCD9XXX_FLYBACK_EN_PWDN_WITH_DELAY			0
#define WCD9XXX_RX_BIAS_FLYB_BUFF			WCD9335_REG(0x6, 0xC7)
#define WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK		GENMASK(7, 4)
#define WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK		GENMASK(3, 0)
#define WCD9XXX_HPH_L_EN				WCD9335_REG(0x6, 0xD3)
#define WCD9XXX_HPH_CONST_SEL_L_MASK			GENMASK(7, 3)
#define WCD9XXX_HPH_CONST_SEL_BYPASS			0
#define WCD9XXX_HPH_CONST_SEL_LP_PATH			0x40
#define WCD9XXX_HPH_CONST_SEL_HQ_PATH			0x80
#define WCD9XXX_HPH_R_EN				WCD9335_REG(0x6, 0xD6)
#define WCD9XXX_HPH_REFBUFF_UHQA_CTL			WCD9335_REG(0x6, 0xDD)
#define WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK		GENMASK(2, 0)
#define WCD9XXX_CLASSH_CTRL_VCL_2                       WCD9335_REG(0x6, 0x9B)
#define WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK	GENMASK(5, 4)
#define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM	0x20
#define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM	0x0
#define WCD9XXX_CDC_RX1_RX_PATH_CTL			WCD9335_REG(0xB, 0x55)
#define WCD9XXX_CDC_RX2_RX_PATH_CTL			WCD9335_REG(0xB, 0x69)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL		WCD9335_REG(0xD, 0x41)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_EN_MASK		BIT(0)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_11P3_EN_MASK	BIT(1)
#define WCD9XXX_CLASSH_CTRL_CCL_1                       WCD9335_REG(0x6, 0x9C)
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK	GENMASK(7, 4)
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA	0x50
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA	0x30

#define WCD9XXX_BASE_ADDRESS				0x3000
#define WCD9XXX_ANA_RX_SUPPLIES				(WCD9XXX_BASE_ADDRESS+0x008)
#define WCD9XXX_ANA_HPH					(WCD9XXX_BASE_ADDRESS+0x009)
#define WCD9XXX_CLASSH_MODE_2				(WCD9XXX_BASE_ADDRESS+0x098)
#define WCD9XXX_CLASSH_MODE_3				(WCD9XXX_BASE_ADDRESS+0x099)
#define WCD9XXX_FLYBACK_VNEG_CTRL_1			(WCD9XXX_BASE_ADDRESS+0x0A5)
#define WCD9XXX_FLYBACK_VNEG_CTRL_4			(WCD9XXX_BASE_ADDRESS+0x0A8)
#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2			(WCD9XXX_BASE_ADDRESS+0x0AF)
#define WCD9XXX_RX_BIAS_HPH_LOWPOWER			(WCD9XXX_BASE_ADDRESS+0x0BF)
#define WCD9XXX_V3_RX_BIAS_FLYB_BUFF			(WCD9XXX_BASE_ADDRESS+0x0C7)
#define WCD9XXX_HPH_PA_CTL1				(WCD9XXX_BASE_ADDRESS+0x0D1)

Annotation

• Immediate include surface: `linux/slab.h`, `sound/soc.h`, `linux/kernel.h`, `linux/delay.h`, `wcd9335.h`, `wcd-clsh-v2.h`.
• Detected declarations: `struct wcd_clsh_ctrl`, `function wcd_enable_clsh_block`, `function wcd_clsh_set_buck_mode`, `function wcd_clsh_v3_set_buck_mode`, `function wcd_clsh_set_flyback_mode`, `function wcd_clsh_buck_ctrl`, `function wcd_clsh_v3_buck_ctrl`, `function wcd_clsh_flyback_ctrl`, `function wcd_clsh_set_gain_path`, `function wcd_clsh_v2_set_hph_mode`.
• Atlas domain: Driver Families / sound/soc.
• Implementation status: integration implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.