sound/soc/codecs/wcd9335.h

Source file repositories/reference/linux-study-clean/sound/soc/codecs/wcd9335.h

File Facts

System: Linux kernel
Corpus path: sound/soc/codecs/wcd9335.h
Extension: .h
Size: 35650 bytes
Lines: 642
Domain: Driver Families
Bucket: sound/soc
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __WCD9335_H__
#define __WCD9335_H__

/*
 * WCD9335 register base can change according to the mode it works in.
 * In slimbus mode the reg base starts from 0x800.
 * In i2s/i2c mode the reg base is 0x0.
 */
#define WCD9335_REG(pg, r)	((pg << 8) | (r))
#define WCD9335_REG_OFFSET(r)	(r & 0xFF)
#define WCD9335_PAGE_OFFSET(r)	((r >> 8) & 0xFF)

/* Page-0 Registers */
#define WCD9335_PAGE0_PAGE_REGISTER		WCD9335_REG(0x00, 0x000)
#define WCD9335_CODEC_RPM_CLK_GATE		WCD9335_REG(0x00, 0x002)
#define WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK	GENMASK(1, 0)
#define WCD9335_CODEC_RPM_CLK_MCLK_CFG		WCD9335_REG(0x00, 0x003)
#define WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ	BIT(0)
#define WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ	BIT(0)
#define WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK	GENMASK(1, 0)
#define WCD9335_CODEC_RPM_RST_CTL		WCD9335_REG(0x00, 0x009)
#define WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL	WCD9335_REG(0x00, 0x011)
#define WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0	WCD9335_REG(0x00, 0x021)
#define WCD9335_CHIP_TIER_CTRL_EFUSE_CTL	WCD9335_REG(0x00, 0x025)
#define WCD9335_CHIP_TIER_CTRL_EFUSE_SSTATE_MASK GENMASK(4, 1)
#define WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK	BIT(0)
#define WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE	BIT(0)
#define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0	WCD9335_REG(0x00, 0x029)
#define WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS	WCD9335_REG(0x00, 0x039)
#define WCD9335_INTR_CFG			WCD9335_REG(0x00, 0x081)
#define WCD9335_INTR_CLR_COMMIT			WCD9335_REG(0x00, 0x082)
#define WCD9335_INTR_PIN1_MASK0			WCD9335_REG(0x00, 0x089)
#define WCD9335_INTR_PIN1_MASK1			WCD9335_REG(0x00, 0x08a)
#define WCD9335_INTR_PIN1_MASK2			WCD9335_REG(0x00, 0x08b)
#define WCD9335_INTR_PIN1_MASK3			WCD9335_REG(0x00, 0x08c)
#define WCD9335_INTR_PIN1_STATUS0		WCD9335_REG(0x00, 0x091)
#define WCD9335_INTR_PIN1_STATUS1		WCD9335_REG(0x00, 0x092)
#define WCD9335_INTR_PIN1_STATUS2		WCD9335_REG(0x00, 0x093)
#define WCD9335_INTR_PIN1_STATUS3		WCD9335_REG(0x00, 0x094)
#define WCD9335_INTR_PIN1_CLEAR0		WCD9335_REG(0x00, 0x099)
#define WCD9335_INTR_PIN1_CLEAR1		WCD9335_REG(0x00, 0x09a)
#define WCD9335_INTR_PIN1_CLEAR2		WCD9335_REG(0x00, 0x09b)
#define WCD9335_INTR_PIN1_CLEAR3		WCD9335_REG(0x00, 0x09c)
#define WCD9335_INTR_PIN2_MASK0			WCD9335_REG(0x00, 0x0a1)
#define WCD9335_INTR_PIN2_MASK1			WCD9335_REG(0x00, 0x0a2)
#define WCD9335_INTR_PIN2_MASK2			WCD9335_REG(0x00, 0x0a3)
#define WCD9335_INTR_PIN2_MASK3			WCD9335_REG(0x00, 0x0a4)
#define WCD9335_INTR_PIN2_STATUS0		WCD9335_REG(0x00, 0x0a9)
#define WCD9335_INTR_PIN2_STATUS1		WCD9335_REG(0x00, 0x0aa)
#define WCD9335_INTR_PIN2_STATUS2		WCD9335_REG(0x00, 0x0ab)
#define WCD9335_INTR_PIN2_STATUS3		WCD9335_REG(0x00, 0x0ac)
#define WCD9335_INTR_PIN2_CLEAR0		WCD9335_REG(0x00, 0x0b1)
#define WCD9335_INTR_PIN2_CLEAR1		WCD9335_REG(0x00, 0x0b2)
#define WCD9335_INTR_PIN2_CLEAR2		WCD9335_REG(0x00, 0x0b3)
#define WCD9335_INTR_PIN2_CLEAR3		WCD9335_REG(0x00, 0x0b4)
#define WCD9335_INTR_LEVEL0			WCD9335_REG(0x00, 0x0e1)
#define WCD9335_INTR_LEVEL1			WCD9335_REG(0x00, 0x0e2)
#define WCD9335_INTR_LEVEL2			WCD9335_REG(0x00, 0x0e3)
#define WCD9335_INTR_LEVEL3			WCD9335_REG(0x00, 0x0e4)

/* Page-1 Registers */
#define WCD9335_CPE_FLL_USER_CTL_0		WCD9335_REG(0x01, 0x001)
#define WCD9335_CPE_FLL_USER_CTL_1		WCD9335_REG(0x01, 0x002)
#define WCD9335_CPE_FLL_USER_CTL_2		WCD9335_REG(0x01, 0x003)
#define WCD9335_CPE_FLL_USER_CTL_3		WCD9335_REG(0x01, 0x004)
#define WCD9335_CPE_FLL_USER_CTL_4		WCD9335_REG(0x01, 0x005)
#define WCD9335_CPE_FLL_USER_CTL_5		WCD9335_REG(0x01, 0x006)
#define WCD9335_CPE_FLL_USER_CTL_6		WCD9335_REG(0x01, 0x007)
#define WCD9335_CPE_FLL_USER_CTL_7		WCD9335_REG(0x01, 0x008)
#define WCD9335_CPE_FLL_USER_CTL_8		WCD9335_REG(0x01, 0x009)
#define WCD9335_CPE_FLL_USER_CTL_9		WCD9335_REG(0x01, 0x00a)
#define WCD9335_CPE_FLL_L_VAL_CTL_0		WCD9335_REG(0x01, 0x00b)
#define WCD9335_CPE_FLL_L_VAL_CTL_1		WCD9335_REG(0x01, 0x00c)
#define WCD9335_CPE_FLL_DSM_FRAC_CTL_0		WCD9335_REG(0x01, 0x00d)
#define WCD9335_CPE_FLL_DSM_FRAC_CTL_1		WCD9335_REG(0x01, 0x00e)
#define WCD9335_CPE_FLL_CONFIG_CTL_0		WCD9335_REG(0x01, 0x00f)
#define WCD9335_CPE_FLL_CONFIG_CTL_1		WCD9335_REG(0x01, 0x010)
#define WCD9335_CPE_FLL_CONFIG_CTL_2		WCD9335_REG(0x01, 0x011)
#define WCD9335_CPE_FLL_CONFIG_CTL_3		WCD9335_REG(0x01, 0x012)
#define WCD9335_CPE_FLL_CONFIG_CTL_4		WCD9335_REG(0x01, 0x013)
#define WCD9335_CPE_FLL_TEST_CTL_0		WCD9335_REG(0x01, 0x014)
#define WCD9335_CPE_FLL_TEST_CTL_1		WCD9335_REG(0x01, 0x015)
#define WCD9335_CPE_FLL_TEST_CTL_2		WCD9335_REG(0x01, 0x016)
#define WCD9335_CPE_FLL_TEST_CTL_3		WCD9335_REG(0x01, 0x017)
#define WCD9335_CPE_FLL_TEST_CTL_4		WCD9335_REG(0x01, 0x018)
#define WCD9335_CPE_FLL_TEST_CTL_5		WCD9335_REG(0x01, 0x019)
#define WCD9335_CPE_FLL_TEST_CTL_6		WCD9335_REG(0x01, 0x01a)
#define WCD9335_CPE_FLL_TEST_CTL_7		WCD9335_REG(0x01, 0x01b)
#define WCD9335_CPE_FLL_FREQ_CTL_0		WCD9335_REG(0x01, 0x01c)
#define WCD9335_CPE_FLL_FREQ_CTL_1		WCD9335_REG(0x01, 0x01d)

Annotation

Atlas domain: Driver Families / sound/soc.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.