sound/soc/fsl/fsl_spdif.c

Source file repositories/reference/linux-study-clean/sound/soc/fsl/fsl_spdif.c

File Facts

System
Linux kernel
Corpus path
sound/soc/fsl/fsl_spdif.c
Extension
.c
Size
50756 bytes
Lines
1775
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct fsl_spdif_soc_data {
	bool imx;
	bool shared_root_clock;
	bool raw_capture_mode;
	bool cchannel_192b;
	u32 interrupts;
	u32 tx_burst;
	u32 rx_burst;
	u64 tx_formats;
};

/*
 * SPDIF control structure
 * Defines channel status, subcode and Q sub
 */
struct spdif_mixer_control {
	/* spinlock to access control data */
	spinlock_t ctl_lock;

	/* IEC958 channel tx status bit */
	unsigned char ch_status[4];

	/* User bits */
	unsigned char subcode[2 * SPDIF_UBITS_SIZE];

	/* Q subcode part of user bits */
	unsigned char qsub[2 * SPDIF_QSUB_SIZE];

	/* Buffer offset for U/Q */
	u32 upos;
	u32 qpos;

	/* Ready buffer index of the two buffers */
	u32 ready_buf;
};

/**
 * struct fsl_spdif_priv - Freescale SPDIF private data
 * @soc: SPDIF soc data
 * @fsl_spdif_control: SPDIF control data
 * @cpu_dai_drv: cpu dai driver
 * @snd_card: sound card pointer
 * @rxrate_kcontrol: kcontrol for RX Sample Rate
 * @pdev: platform device pointer
 * @regmap: regmap handler
 * @dpll_locked: dpll lock flag
 * @txrate: the best rates for playback
 * @txclk_df: STC_TXCLK_DF dividers value for playback
 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
 * @txclk_src: STC_TXCLK_SRC values for playback
 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
 * @txclk: tx clock sources for playback
 * @rxclk: rx clock sources for capture
 * @coreclk: core clock for register access via DMA
 * @sysclk: system clock for rx clock rate measurement
 * @spbaclk: SPBA clock (optional, depending on SoC design)
 * @dma_params_tx: DMA parameters for transmit channel
 * @dma_params_rx: DMA parameters for receive channel
 * @regcache_srpc: regcache for SRPC
 * @bypass: status of bypass input to output
 * @pll8k_clk: PLL clock for the rate of multiply of 8kHz
 * @pll11k_clk: PLL clock for the rate of multiply of 11kHz
 */
struct fsl_spdif_priv {
	const struct fsl_spdif_soc_data *soc;
	struct spdif_mixer_control fsl_spdif_control;
	struct snd_soc_dai_driver cpu_dai_drv;
	struct snd_card *snd_card;
	struct snd_kcontrol *rxrate_kcontrol;
	struct platform_device *pdev;
	struct regmap *regmap;
	bool dpll_locked;
	u32 txrate[SPDIF_TXRATE_MAX];
	u8 txclk_df[SPDIF_TXRATE_MAX];
	u16 sysclk_df[SPDIF_TXRATE_MAX];
	u8 txclk_src[SPDIF_TXRATE_MAX];
	u8 rxclk_src;
	struct clk *txclk[STC_TXCLK_SRC_MAX];
	struct clk *rxclk;
	struct clk *coreclk;
	struct clk *sysclk;
	struct clk *spbaclk;
	struct snd_dmaengine_dai_dma_data dma_params_tx;
	struct snd_dmaengine_dai_dma_data dma_params_rx;
	/* regcache for SRPC */
	u32 regcache_srpc;
	bool bypass;
	struct clk *pll8k_clk;
	struct clk *pll11k_clk;
};

Annotation

Implementation Notes