sound/soc/fsl/fsl_spdif.h

Source file repositories/reference/linux-study-clean/sound/soc/fsl/fsl_spdif.h

File Facts

System
Linux kernel
Corpus path
sound/soc/fsl/fsl_spdif.h
Extension
.h
Size
8996 bytes
Lines
221
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _FSL_SPDIF_DAI_H
#define _FSL_SPDIF_DAI_H

/* S/PDIF Register Map */
#define REG_SPDIF_SCR 			0x0	/* SPDIF Configuration Register */
#define REG_SPDIF_SRCD		 	0x4	/* CDText Control Register */
#define REG_SPDIF_SRPC			0x8	/* PhaseConfig Register */
#define REG_SPDIF_SIE			0xc	/* InterruptEn Register */
#define REG_SPDIF_SIS			0x10	/* InterruptStat Register */
#define REG_SPDIF_SIC			0x10	/* InterruptClear Register */
#define REG_SPDIF_SRL			0x14	/* SPDIFRxLeft Register */
#define REG_SPDIF_SRR			0x18	/* SPDIFRxRight Register */
#define REG_SPDIF_SRCSH			0x1c	/* SPDIFRxCChannel_h Register */
#define REG_SPDIF_SRCSL			0x20	/* SPDIFRxCChannel_l Register */
#define REG_SPDIF_SRU			0x24	/* UchannelRx Register */
#define REG_SPDIF_SRQ			0x28	/* QchannelRx Register */
#define REG_SPDIF_STL			0x2C	/* SPDIFTxLeft Register */
#define REG_SPDIF_STR			0x30	/* SPDIFTxRight Register */
#define REG_SPDIF_STCSCH		0x34	/* SPDIFTxCChannelCons_h Register */
#define REG_SPDIF_STCSCL		0x38	/* SPDIFTxCChannelCons_l Register */
#define REG_SPDIF_STCSPH		0x3C	/* SPDIFTxCChannel_Prof_h Register */
#define REG_SPDIF_STCSPL		0x40	/* SPDIFTxCChannel_Prof_l Register */
#define REG_SPDIF_SRFM			0x44	/* FreqMeas Register */
#define REG_SPDIF_STC			0x50	/* SPDIFTxClk Register */

#define REG_SPDIF_SRCCA_31_0		0x60	/* SPDIF receive C channel register, bits 31-0 */
#define REG_SPDIF_SRCCA_63_32		0x64	/* SPDIF receive C channel register, bits 63-32 */
#define REG_SPDIF_SRCCA_95_64		0x68	/* SPDIF receive C channel register, bits 95-64 */
#define REG_SPDIF_SRCCA_127_96		0x6C	/* SPDIF receive C channel register, bits 127-96 */
#define REG_SPDIF_SRCCA_159_128		0x70	/* SPDIF receive C channel register, bits 159-128 */
#define REG_SPDIF_SRCCA_191_160		0x74	/* SPDIF receive C channel register, bits 191-160 */
#define REG_SPDIF_STCCA_31_0		0x78	/* SPDIF transmit C channel register, bits 31-0 */
#define REG_SPDIF_STCCA_63_32		0x7C	/* SPDIF transmit C channel register, bits 63-32 */
#define REG_SPDIF_STCCA_95_64		0x80	/* SPDIF transmit C channel register, bits 95-64 */
#define REG_SPDIF_STCCA_127_96		0x84	/* SPDIF transmit C channel register, bits 127-96 */
#define REG_SPDIF_STCCA_159_128		0x88	/* SPDIF transmit C channel register, bits 159-128 */
#define REG_SPDIF_STCCA_191_160		0x8C	/* SPDIF transmit C channel register, bits 191-160 */

/* SPDIF Configuration register */
#define SCR_RXFIFO_CTL_OFFSET		23
#define SCR_RXFIFO_CTL_MASK		(1 << SCR_RXFIFO_CTL_OFFSET)
#define SCR_RXFIFO_CTL_ZERO		(1 << SCR_RXFIFO_CTL_OFFSET)
#define SCR_RXFIFO_OFF_OFFSET		22
#define SCR_RXFIFO_OFF_MASK		(1 << SCR_RXFIFO_OFF_OFFSET)
#define SCR_RXFIFO_OFF			(1 << SCR_RXFIFO_OFF_OFFSET)
#define SCR_RXFIFO_RST_OFFSET		21
#define SCR_RXFIFO_RST_MASK		(1 << SCR_RXFIFO_RST_OFFSET)
#define SCR_RXFIFO_RST			(1 << SCR_RXFIFO_RST_OFFSET)
#define SCR_RXFIFO_FSEL_OFFSET		19
#define SCR_RXFIFO_FSEL_MASK		(0x3 << SCR_RXFIFO_FSEL_OFFSET)
#define SCR_RXFIFO_FSEL_IF0		(0x0 << SCR_RXFIFO_FSEL_OFFSET)
#define SCR_RXFIFO_FSEL_IF4		(0x1 << SCR_RXFIFO_FSEL_OFFSET)
#define SCR_RXFIFO_FSEL_IF8		(0x2 << SCR_RXFIFO_FSEL_OFFSET)
#define SCR_RXFIFO_FSEL_IF12		(0x3 << SCR_RXFIFO_FSEL_OFFSET)
#define SCR_RXFIFO_AUTOSYNC_OFFSET	18
#define SCR_RXFIFO_AUTOSYNC_MASK	(1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
#define SCR_RXFIFO_AUTOSYNC		(1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
#define SCR_TXFIFO_AUTOSYNC_OFFSET	17
#define SCR_TXFIFO_AUTOSYNC_MASK	(1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
#define SCR_TXFIFO_AUTOSYNC		(1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
#define SCR_TXFIFO_FSEL_OFFSET		15
#define SCR_TXFIFO_FSEL_MASK		(0x3 << SCR_TXFIFO_FSEL_OFFSET)
#define SCR_TXFIFO_FSEL_IF0		(0x0 << SCR_TXFIFO_FSEL_OFFSET)
#define SCR_TXFIFO_FSEL_IF4		(0x1 << SCR_TXFIFO_FSEL_OFFSET)
#define SCR_TXFIFO_FSEL_IF8		(0x2 << SCR_TXFIFO_FSEL_OFFSET)
#define SCR_TXFIFO_FSEL_IF12		(0x3 << SCR_TXFIFO_FSEL_OFFSET)
#define SCR_RAW_CAPTURE_MODE		BIT(14)
#define SCR_LOW_POWER			(1 << 13)
#define SCR_SOFT_RESET			(1 << 12)
#define SCR_TXFIFO_CTRL_OFFSET		10
#define SCR_TXFIFO_CTRL_MASK		(0x3 << SCR_TXFIFO_CTRL_OFFSET)
#define SCR_TXFIFO_CTRL_ZERO		(0x0 << SCR_TXFIFO_CTRL_OFFSET)
#define SCR_TXFIFO_CTRL_NORMAL		(0x1 << SCR_TXFIFO_CTRL_OFFSET)
#define SCR_TXFIFO_CTRL_ONESAMPLE	(0x2 << SCR_TXFIFO_CTRL_OFFSET)
#define SCR_DMA_RX_EN_OFFSET		9
#define SCR_DMA_RX_EN_MASK		(1 << SCR_DMA_RX_EN_OFFSET)
#define SCR_DMA_RX_EN			(1 << SCR_DMA_RX_EN_OFFSET)
#define SCR_DMA_TX_EN_OFFSET		8
#define SCR_DMA_TX_EN_MASK		(1 << SCR_DMA_TX_EN_OFFSET)
#define SCR_DMA_TX_EN			(1 << SCR_DMA_TX_EN_OFFSET)
#define SCR_VAL_OFFSET			5
#define SCR_VAL_MASK			(1 << SCR_VAL_OFFSET)
#define SCR_VAL_CLEAR			(1 << SCR_VAL_OFFSET)
#define SCR_TXSEL_OFFSET		2
#define SCR_TXSEL_MASK			(0x7 << SCR_TXSEL_OFFSET)
#define SCR_TXSEL_OFF			(0 << SCR_TXSEL_OFFSET)
#define SCR_TXSEL_RX			(1 << SCR_TXSEL_OFFSET)
#define SCR_TXSEL_NORMAL		(0x5 << SCR_TXSEL_OFFSET)
#define SCR_USRC_SEL_OFFSET		0x0
#define SCR_USRC_SEL_MASK		(0x3 << SCR_USRC_SEL_OFFSET)

Annotation

Implementation Notes