sound/soc/fsl/fsl_xcvr.c

Source file repositories/reference/linux-study-clean/sound/soc/fsl/fsl_xcvr.c

File Facts

System
Linux kernel
Corpus path
sound/soc/fsl/fsl_xcvr.c
Extension
.c
Size
58149 bytes
Lines
1934
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct fsl_xcvr_soc_data {
	const char *fw_name;
	bool spdif_only;
	bool use_edma;
	bool use_phy;
	enum fsl_xcvr_pll_verison pll_ver;
};

struct fsl_xcvr {
	const struct fsl_xcvr_soc_data *soc_data;
	struct platform_device *pdev;
	struct regmap *regmap;
	struct regmap *regmap_phy;
	struct regmap *regmap_pll;
	struct clk *ipg_clk;
	struct clk *pll_ipg_clk;
	struct clk *phy_clk;
	struct clk *spba_clk;
	struct clk *pll8k_clk;
	struct clk *pll11k_clk;
	struct reset_control *reset;
	u8 streams;
	u32 mode;
	u32 arc_mode;
	void __iomem *ram_addr;
	struct snd_dmaengine_dai_dma_data dma_prms_rx;
	struct snd_dmaengine_dai_dma_data dma_prms_tx;
	struct snd_aes_iec958 rx_iec958;
	struct snd_aes_iec958 tx_iec958;
	u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
	struct work_struct work_rst;
	spinlock_t lock; /* Protect hw_reset and trigger */
	struct snd_pcm_hw_constraint_list spdif_constr_rates;
	u32 spdif_constr_rates_list[SPDIF_NUM_RATES];
};

static const char * const inc_mode[] = {
	"On enabled and bitcount increment", "On enabled"
};

static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum,
			    FSL_XCVR_TX_DPTH_CNTR_CTRL,
			    FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode);
static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum,
			    FSL_XCVR_RX_DPTH_CNTR_CTRL,
			    FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode);

static const struct snd_kcontrol_new fsl_xcvr_timestamp_ctrls[] = {
	FSL_ASOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL,
			    FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0,
			    fsl_asoc_get_volsw, fsl_asoc_put_volsw),
	FSL_ASOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum,
			  fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
	FSL_ASOC_SINGLE_EXT("Transmit Timestamp Reset Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL,
			    FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0,
			    fsl_asoc_get_volsw, fsl_asoc_put_volsw),
	FSL_ASOC_SINGLE_EXT("Transmit Bit Counter Reset Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL,
			    FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0,
			    fsl_asoc_get_volsw, fsl_asoc_put_volsw),
	FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_XCVR_TX_DPTH_TSCR,
				     1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
	FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_XCVR_TX_DPTH_BCR,
				     1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
	FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Count Timestamp", FSL_XCVR_TX_DPTH_BCTR,
				     1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
	FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_XCVR_TX_DPTH_BCRR,
				     1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
	FSL_ASOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL,
			    FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0,
			    fsl_asoc_get_volsw, fsl_asoc_put_volsw),
	FSL_ASOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum,
			  fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
	FSL_ASOC_SINGLE_EXT("Receive Timestamp Reset Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL,
			    FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0,
			    fsl_asoc_get_volsw, fsl_asoc_put_volsw),
	FSL_ASOC_SINGLE_EXT("Receive Bit Counter Reset Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL,
			    FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0,
			    fsl_asoc_get_volsw, fsl_asoc_put_volsw),
	FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_XCVR_RX_DPTH_TSCR,
				     1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
	FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_XCVR_RX_DPTH_BCR,
				     1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
	FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Count Timestamp", FSL_XCVR_RX_DPTH_BCTR,
				     1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
	FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_XCVR_RX_DPTH_BCRR,
				     1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
};

static const struct fsl_xcvr_pll_conf {
	u8 mfi;   /* min=0x18, max=0x38 */

Annotation

Implementation Notes