sound/soc/fsl/fsl_xcvr.h

Source file repositories/reference/linux-study-clean/sound/soc/fsl/fsl_xcvr.h

File Facts

System
Linux kernel
Corpus path
sound/soc/fsl/fsl_xcvr.h
Extension
.h
Size
16782 bytes
Lines
422
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __FSL_XCVR_H
#define __FSL_XCVR_H

#define FSL_XCVR_MODE_SPDIF	0
#define FSL_XCVR_MODE_ARC	1
#define FSL_XCVR_MODE_EARC	2

/* XCVR Registers */
#define FSL_XCVR_REG_OFFSET		0x800 /* regs offset */
#define FSL_XCVR_FIFO_SIZE		0x80  /* 128 */
#define FSL_XCVR_FIFO_WMK_RX		(FSL_XCVR_FIFO_SIZE >> 1)   /* 64 */
#define FSL_XCVR_FIFO_WMK_TX		(FSL_XCVR_FIFO_SIZE >> 1)   /* 64 */
#define FSL_XCVR_MAXBURST_RX		(FSL_XCVR_FIFO_WMK_RX >> 2) /* 16 */
#define FSL_XCVR_MAXBURST_TX		(FSL_XCVR_FIFO_WMK_TX >> 2) /* 16 */

#define FSL_XCVR_RX_FIFO_ADDR		0x0C00
#define FSL_XCVR_TX_FIFO_ADDR		0x0E00

#define FSL_XCVR_VERSION		0x00  /* Version */
#define FSL_XCVR_EXT_CTRL		0x10  /* Control */
#define FSL_XCVR_EXT_STATUS		0x20  /* Status */
#define FSL_XCVR_EXT_IER0		0x30  /* Interrupt en 0 */
#define FSL_XCVR_EXT_IER1		0x40  /* Interrupt en 1 */
#define FSL_XCVR_EXT_ISR		0x50  /* Interrupt status */
#define FSL_XCVR_EXT_ISR_SET		0x54  /* Interrupt status */
#define FSL_XCVR_EXT_ISR_CLR		0x58  /* Interrupt status */
#define FSL_XCVR_EXT_ISR_TOG		0x5C  /* Interrupt status */
#define FSL_XCVR_IER			0x70  /* Interrupt en for M0+ */
#define FSL_XCVR_ISR			0x80  /* Interrupt status */
#define FSL_XCVR_ISR_SET		0x84  /* Interrupt status set */
#define FSL_XCVR_ISR_CLR		0x88  /* Interrupt status clear */
#define FSL_XCVR_ISR_TOG		0x8C  /* Interrupt status toggle */
#define FSL_XCVR_PHY_AI_CTRL		0x90
#define FSL_XCVR_PHY_AI_CTRL_SET	0x94
#define FSL_XCVR_PHY_AI_CTRL_CLR	0x98
#define FSL_XCVR_PHY_AI_CTRL_TOG	0x9C
#define FSL_XCVR_PHY_AI_WDATA		0xA0
#define FSL_XCVR_PHY_AI_RDATA		0xA4
#define FSL_XCVR_CLK_CTRL		0xB0
#define FSL_XCVR_RX_DPTH_CTRL		0x180 /* RX datapath ctrl reg */
#define FSL_XCVR_RX_DPTH_CTRL_SET	0x184
#define FSL_XCVR_RX_DPTH_CTRL_CLR	0x188
#define FSL_XCVR_RX_DPTH_CTRL_TOG	0x18c

#define FSL_XCVR_RX_CS_DATA_0		0x190
#define FSL_XCVR_RX_CS_DATA_1		0x194
#define FSL_XCVR_RX_CS_DATA_2		0x198
#define FSL_XCVR_RX_CS_DATA_3		0x19C
#define FSL_XCVR_RX_CS_DATA_4		0x1A0
#define FSL_XCVR_RX_CS_DATA_5		0x1A4

#define FSL_XCVR_RX_DPTH_CNTR_CTRL	0x1C0
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_SET	0x1C4
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR	0x1C8
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG	0x1CC

#define FSL_XCVR_RX_DPTH_TSCR		0x1D0
#define FSL_XCVR_RX_DPTH_BCR		0x1D4
#define FSL_XCVR_RX_DPTH_BCTR		0x1D8
#define FSL_XCVR_RX_DPTH_BCRR		0x1DC

#define FSL_XCVR_TX_DPTH_CTRL		0x220 /* TX datapath ctrl reg */
#define FSL_XCVR_TX_DPTH_CTRL_SET	0x224
#define FSL_XCVR_TX_DPTH_CTRL_CLR	0x228
#define FSL_XCVR_TX_DPTH_CTRL_TOG	0x22C
#define FSL_XCVR_TX_CS_DATA_0		0x230 /* TX channel status bits regs */
#define FSL_XCVR_TX_CS_DATA_1		0x234
#define FSL_XCVR_TX_CS_DATA_2		0x238
#define FSL_XCVR_TX_CS_DATA_3		0x23C
#define FSL_XCVR_TX_CS_DATA_4		0x240
#define FSL_XCVR_TX_CS_DATA_5		0x244

#define FSL_XCVR_TX_DPTH_CNTR_CTRL	0x260
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_SET	0x264
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR	0x268
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG	0x26C

#define FSL_XCVR_TX_DPTH_TSCR		0x270
#define FSL_XCVR_TX_DPTH_BCR		0x274
#define FSL_XCVR_TX_DPTH_BCTR		0x278
#define FSL_XCVR_TX_DPTH_BCRR		0x27C

#define FSL_XCVR_DEBUG_REG_0		0x2E0
#define FSL_XCVR_DEBUG_REG_1		0x2F0

#define FSL_XCVR_MAX_REG		FSL_XCVR_DEBUG_REG_1

#define FSL_XCVR_EXT_CTRL_CORE_RESET	BIT(31)

#define FSL_XCVR_EXT_CTRL_RX_CMDC_RESET	BIT(30)

Annotation

Implementation Notes