sound/soc/intel/catpt/registers.h

Source file repositories/reference/linux-study-clean/sound/soc/intel/catpt/registers.h

File Facts

System
Linux kernel
Corpus path
sound/soc/intel/catpt/registers.h
Extension
.h
Size
6282 bytes
Lines
193
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SND_SOC_INTEL_CATPT_REGS_H
#define __SND_SOC_INTEL_CATPT_REGS_H

#include <linux/bitops.h>
#include <linux/iopoll.h>
#include <uapi/linux/pci_regs.h>

#define CATPT_SHIM_REGS_SIZE	4096
#define CATPT_DMA_REGS_SIZE	1024
#define CATPT_DMA_COUNT		2
#define CATPT_SSP_REGS_SIZE	512

/* DSP Shim registers */

#define CATPT_SHIM_CS1		0x00
#define CATPT_SHIM_ISC		0x18
#define CATPT_SHIM_ISD		0x20
#define CATPT_SHIM_IMC		0x28
#define CATPT_SHIM_IMD		0x30
#define CATPT_SHIM_IPCC		0x38
#define CATPT_SHIM_IPCD		0x40
#define CATPT_SHIM_CLKCTL	0x78
#define CATPT_SHIM_CS2		0x80
#define CATPT_SHIM_LTRC		0xE0
#define CATPT_SHIM_HMDC		0xE8

#define CATPT_CS_LPCS		BIT(31)
#define CATPT_CS_SFCR(ssp)	BIT(27 + (ssp))
#define CATPT_CS_S1IOCS		BIT(23)
#define CATPT_CS_S0IOCS		BIT(21)
#define CATPT_CS_PCE		BIT(15)
#define CATPT_CS_SDPM(ssp)	BIT(11 + (ssp))
#define CATPT_CS_STALL		BIT(10)
#define CATPT_CS_DCS		GENMASK(6, 4)
/* b100 DSP core & audio fabric high clock */
#define CATPT_CS_DCS_HIGH	(0x4 << 4)
#define CATPT_CS_SBCS(ssp)	BIT(2 + (ssp))
#define CATPT_CS_RST		BIT(1)

#define CATPT_ISC_IPCDB		BIT(1)
#define CATPT_ISC_IPCCD		BIT(0)
#define CATPT_ISD_DCPWM		BIT(31)
#define CATPT_ISD_IPCCB		BIT(1)
#define CATPT_ISD_IPCDD		BIT(0)

#define CATPT_IMC_IPCDB		BIT(1)
#define CATPT_IMC_IPCCD		BIT(0)
#define CATPT_IMD_IPCCB		BIT(1)
#define CATPT_IMD_IPCDD		BIT(0)

#define CATPT_IPCC_BUSY		BIT(31)
#define CATPT_IPCC_DONE		BIT(30)
#define CATPT_IPCD_BUSY		BIT(31)
#define CATPT_IPCD_DONE		BIT(30)

#define CATPT_CLKCTL_CFCIP	BIT(31)
#define CATPT_CLKCTL_SMOS	GENMASK(25, 24)

#define CATPT_HMDC_HDDA(e, ch)	BIT(8 * (e) + (ch))

/* defaults to reset SHIM registers to after each power cycle */
#define CATPT_CS_DEFAULT	0x8480040E
#define CATPT_ISC_DEFAULT	0x0
#define CATPT_ISD_DEFAULT	0x0
#define CATPT_IMC_DEFAULT	0x7FFF0003
#define CATPT_IMD_DEFAULT	0x7FFF0003
#define CATPT_IPCC_DEFAULT	0x0
#define CATPT_IPCD_DEFAULT	0x0
#define CATPT_CLKCTL_DEFAULT	0x7FF
#define CATPT_CS2_DEFAULT	0x0
#define CATPT_LTRC_DEFAULT	0x0
#define CATPT_HMDC_DEFAULT	0x0

/* PCI Configuration registers */

#define CATPT_PCI_PMCAPID	0x80
#define CATPT_PCI_PMCS		(CATPT_PCI_PMCAPID + PCI_PM_CTRL)
#define CATPT_PCI_VDRTCTL0	0xA0
#define CATPT_PCI_VDRTCTL2	0xA8

#define CATPT_VDRTCTL2_DTCGE	BIT(10)
#define CATPT_VDRTCTL2_DCLCGE	BIT(1)
#define CATPT_VDRTCTL2_CGEALL	0xF7F

/* LPT PCI Configuration bits */

#define LPT_VDRTCTL0_DSRAMPGE(b)	BIT(16 + (b))
#define LPT_VDRTCTL0_DSRAMPGE_MASK	GENMASK(31, 16)
#define LPT_VDRTCTL0_ISRAMPGE(b)	BIT(6 + (b))
#define LPT_VDRTCTL0_ISRAMPGE_MASK	GENMASK(15, 6)

Annotation

Implementation Notes