sound/soc/mediatek/mt7986/mt7986-reg.h

Source file repositories/reference/linux-study-clean/sound/soc/mediatek/mt7986/mt7986-reg.h

File Facts

System: Linux kernel
Corpus path: sound/soc/mediatek/mt7986/mt7986-reg.h
Extension: .h
Size: 7920 bytes
Lines: 197
Domain: Driver Families
Bucket: sound/soc
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _MT7986_REG_H_
#define _MT7986_REG_H_

#define AUDIO_TOP_CON2                  0x0008
#define AUDIO_TOP_CON4                  0x0010
#define AUDIO_ENGEN_CON0                0x0014
#define AFE_IRQ_MCU_EN                  0x0100
#define AFE_IRQ_MCU_STATUS              0x0120
#define AFE_IRQ_MCU_CLR                 0x0128
#define AFE_IRQ0_MCU_CFG0               0x0140
#define AFE_IRQ0_MCU_CFG1               0x0144
#define AFE_IRQ1_MCU_CFG0               0x0148
#define AFE_IRQ1_MCU_CFG1               0x014c
#define AFE_IRQ2_MCU_CFG0               0x0150
#define AFE_IRQ2_MCU_CFG1               0x0154
#define ETDM_IN5_CON0                   0x13f0
#define ETDM_IN5_CON1                   0x13f4
#define ETDM_IN5_CON2                   0x13f8
#define ETDM_IN5_CON3                   0x13fc
#define ETDM_IN5_CON4                   0x1400
#define ETDM_OUT5_CON0                  0x1570
#define ETDM_OUT5_CON4                  0x1580
#define ETDM_OUT5_CON5                  0x1584
#define ETDM_4_7_COWORK_CON0            0x15e0
#define ETDM_4_7_COWORK_CON1            0x15e4
#define AFE_CONN018_1                   0x1b44
#define AFE_CONN018_4                   0x1b50
#define AFE_CONN019_1                   0x1b64
#define AFE_CONN019_4                   0x1b70
#define AFE_CONN124_1                   0x2884
#define AFE_CONN124_4                   0x2890
#define AFE_CONN125_1                   0x28a4
#define AFE_CONN125_4                   0x28b0
#define AFE_CONN_RS_0                   0x3920
#define AFE_CONN_RS_3                   0x392c
#define AFE_CONN_16BIT_0                0x3960
#define AFE_CONN_16BIT_3                0x396c
#define AFE_CONN_24BIT_0                0x3980
#define AFE_CONN_24BIT_3                0x398c
#define AFE_MEMIF_CON0                  0x3d98
#define AFE_MEMIF_RD_MON                0x3da0
#define AFE_MEMIF_WR_MON                0x3da4
#define AFE_DL0_BASE_MSB                0x3e40
#define AFE_DL0_BASE                    0x3e44
#define AFE_DL0_CUR_MSB                 0x3e48
#define AFE_DL0_CUR                     0x3e4c
#define AFE_DL0_END_MSB                 0x3e50
#define AFE_DL0_END                     0x3e54
#define AFE_DL0_RCH_MON                 0x3e58
#define AFE_DL0_LCH_MON                 0x3e5c
#define AFE_DL0_CON0                    0x3e60
#define AFE_VUL0_BASE_MSB               0x4220
#define AFE_VUL0_BASE                   0x4224
#define AFE_VUL0_CUR_MSB                0x4228
#define AFE_VUL0_CUR                    0x422c
#define AFE_VUL0_END_MSB                0x4230
#define AFE_VUL0_END                    0x4234
#define AFE_VUL0_CON0                   0x4238

#define AFE_MAX_REGISTER AFE_VUL0_CON0
#define AFE_IRQ_STATUS_BITS             0x7
#define AFE_IRQ_CNT_SHIFT               0
#define AFE_IRQ_CNT_MASK	        0xffffff

/* AUDIO_TOP_CON2 */
#define CLK_OUT5_PDN                    BIT(14)
#define CLK_OUT5_PDN_MASK               BIT(14)
#define CLK_IN5_PDN                     BIT(7)
#define CLK_IN5_PDN_MASK                BIT(7)

/* AUDIO_TOP_CON4 */
#define PDN_APLL_TUNER2                 BIT(12)
#define PDN_APLL_TUNER2_MASK            BIT(12)

/* AUDIO_ENGEN_CON0 */
#define AUD_APLL2_EN                    BIT(3)
#define AUD_APLL2_EN_MASK               BIT(3)
#define AUD_26M_EN                      BIT(0)
#define AUD_26M_EN_MASK                 BIT(0)

/* AFE_DL0_CON0 */
#define DL0_ON_SFT                      28
#define DL0_ON_MASK                     0x1
#define DL0_ON_MASK_SFT                 BIT(28)
#define DL0_MINLEN_SFT                  20
#define DL0_MINLEN_MASK                 0xf
#define DL0_MINLEN_MASK_SFT             (0xf << 20)
#define DL0_MODE_SFT                    8
#define DL0_MODE_MASK                   0x1f
#define DL0_MODE_MASK_SFT               (0x1f << 8)

Annotation

Atlas domain: Driver Families / sound/soc.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.