sound/soc/mediatek/mt8186/mt8186-dai-adda.c
Source file repositories/reference/linux-study-clean/sound/soc/mediatek/mt8186/mt8186-dai-adda.c
File Facts
- System
- Linux kernel
- Corpus path
sound/soc/mediatek/mt8186/mt8186-dai-adda.c- Extension
.c- Size
- 22976 bytes
- Lines
- 777
- Domain
- Driver Families
- Bucket
- sound/soc
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/regmap.hlinux/delay.hmt8186-afe-clk.hmt8186-afe-common.hmt8186-afe-gpio.hmt8186-interconnection.h../common/mtk-dai-adda-common.h
Detected Declarations
struct mtk_afe_adda_privfunction mtk_adda_ul_src_dmicfunction mtk_adda_ul_eventfunction mtk_adda_pad_top_eventfunction mtk_adda_mtkaif_cfg_eventfunction mtk_adda_dl_eventfunction mt8186_adda_dmic_getfunction mt8186_adda_dmic_setfunction mtk_afe_dac_hires_connectfunction mtk_afe_adc_hires_connectfunction mtk_dai_adda_hw_paramsfunction mt8186_dai_adda_register
Annotated Snippet
struct mtk_afe_adda_priv {
int dl_rate;
int ul_rate;
};
static struct mtk_afe_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe,
const char *name)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id;
if (strncmp(name, "aud_dac", 7) == 0 || strncmp(name, "aud_adc", 7) == 0)
dai_id = MT8186_DAI_ADDA;
else
return NULL;
return afe_priv->dai_priv[dai_id];
}
/* dai component */
static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN3, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN3, I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN3, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN3, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN3_1, I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN3_1, I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN3_1, I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN3_1, I_DL8_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN3,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN3,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN3,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN3,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1 Switch", AFE_CONN3,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN3_1,
I_SRC_1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1 Switch", AFE_CONN3_1,
I_SRC_2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN4, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN4, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN4, I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN4, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN4, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN4, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN4, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN4_1, I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN4_1, I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN4_1, I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN4_1, I_DL8_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN4,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN4,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN4,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN4,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN4,
I_PCM_2_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN4_1,
I_SRC_1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2 Switch", AFE_CONN4_1,
I_SRC_2_OUT_CH2, 1, 0),
};
enum {
SUPPLY_SEQ_ADDA_AFE_ON,
SUPPLY_SEQ_ADDA_DL_ON,
SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SUPPLY_SEQ_ADDA_FIFO,
SUPPLY_SEQ_ADDA_AP_DMIC,
SUPPLY_SEQ_ADDA_UL_ON,
};
static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)
{
unsigned int reg;
switch (id) {
case MT8186_DAI_ADDA:
case MT8186_DAI_AP_DMIC:
Annotation
- Immediate include surface: `linux/regmap.h`, `linux/delay.h`, `mt8186-afe-clk.h`, `mt8186-afe-common.h`, `mt8186-afe-gpio.h`, `mt8186-interconnection.h`, `../common/mtk-dai-adda-common.h`.
- Detected declarations: `struct mtk_afe_adda_priv`, `function mtk_adda_ul_src_dmic`, `function mtk_adda_ul_event`, `function mtk_adda_pad_top_event`, `function mtk_adda_mtkaif_cfg_event`, `function mtk_adda_dl_event`, `function mt8186_adda_dmic_get`, `function mt8186_adda_dmic_set`, `function mtk_afe_dac_hires_connect`, `function mtk_afe_adc_hires_connect`.
- Atlas domain: Driver Families / sound/soc.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.