sound/soc/mediatek/mt8189/mt8189-afe-clk.c

Source file repositories/reference/linux-study-clean/sound/soc/mediatek/mt8189/mt8189-afe-clk.c

File Facts

System
Linux kernel
Corpus path
sound/soc/mediatek/mt8189/mt8189-afe-clk.c
Extension
.c
Size
20642 bytes
Lines
751
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mt8189_mck_div {
	int m_sel_id;
	int div_clk_id;
};

static const struct mt8189_mck_div mck_div[MT8189_MCK_NUM] = {
	[MT8189_I2SIN0_MCK] = {
		.m_sel_id = MT8189_CLK_TOP_I2SIN0_M_SEL,
		.div_clk_id = MT8189_CLK_TOP_APLL12_DIV_I2SIN0,
	},
	[MT8189_I2SIN1_MCK] = {
		.m_sel_id = MT8189_CLK_TOP_I2SIN1_M_SEL,
		.div_clk_id = MT8189_CLK_TOP_APLL12_DIV_I2SIN1,
	},
	[MT8189_I2SOUT0_MCK] = {
		.m_sel_id = MT8189_CLK_TOP_I2SOUT0_M_SEL,
		.div_clk_id = MT8189_CLK_TOP_APLL12_DIV_I2SOUT0,
	},
	[MT8189_I2SOUT1_MCK] = {
		.m_sel_id = MT8189_CLK_TOP_I2SOUT1_M_SEL,
		.div_clk_id = MT8189_CLK_TOP_APLL12_DIV_I2SOUT1,
	},
	[MT8189_FMI2S_MCK] = {
		.m_sel_id = MT8189_CLK_TOP_FMI2S_M_SEL,
		.div_clk_id = MT8189_CLK_TOP_APLL12_DIV_FMI2S,
	},
	[MT8189_TDMOUT_MCK] = {
		.m_sel_id = MT8189_CLK_TOP_TDMOUT_M_SEL,
		.div_clk_id = MT8189_CLK_TOP_APLL12_DIV_TDMOUT_M,
	},
	[MT8189_TDMOUT_BCK] = {
		.m_sel_id = -1,
		.div_clk_id = MT8189_CLK_TOP_APLL12_DIV_TDMOUT_B,
	},
};

static const char *aud_clks[MT8189_CLK_NUM] = {
	[MT8189_CLK_TOP_MUX_AUDIOINTBUS] = "top_aud_intbus",
	[MT8189_CLK_TOP_MUX_AUD_ENG1] = "top_aud_eng1",
	[MT8189_CLK_TOP_MUX_AUD_ENG2] = "top_aud_eng2",
	[MT8189_CLK_TOP_MUX_AUDIO_H] = "top_aud_h",
	/* pll */
	[MT8189_CLK_TOP_APLL1_CK] = "apll1",
	[MT8189_CLK_TOP_APLL2_CK] = "apll2",
	/* divider */
	[MT8189_CLK_TOP_APLL1_D4] = "apll1_d4",
	[MT8189_CLK_TOP_APLL2_D4] = "apll2_d4",
	[MT8189_CLK_TOP_APLL12_DIV_I2SIN0] = "apll12_div_i2sin0",
	[MT8189_CLK_TOP_APLL12_DIV_I2SIN1] = "apll12_div_i2sin1",
	[MT8189_CLK_TOP_APLL12_DIV_I2SOUT0] = "apll12_div_i2sout0",
	[MT8189_CLK_TOP_APLL12_DIV_I2SOUT1] = "apll12_div_i2sout1",
	[MT8189_CLK_TOP_APLL12_DIV_FMI2S] = "apll12_div_fmi2s",
	[MT8189_CLK_TOP_APLL12_DIV_TDMOUT_M] = "apll12_div_tdmout_m",
	[MT8189_CLK_TOP_APLL12_DIV_TDMOUT_B] = "apll12_div_tdmout_b",
	/* mux */
	[MT8189_CLK_TOP_MUX_AUD_1] = "top_apll1",
	[MT8189_CLK_TOP_MUX_AUD_2] = "top_apll2",
	[MT8189_CLK_TOP_I2SIN0_M_SEL] = "top_i2sin0",
	[MT8189_CLK_TOP_I2SIN1_M_SEL] = "top_i2sin1",
	[MT8189_CLK_TOP_I2SOUT0_M_SEL] = "top_i2sout0",
	[MT8189_CLK_TOP_I2SOUT1_M_SEL] = "top_i2sout1",
	[MT8189_CLK_TOP_FMI2S_M_SEL] = "top_fmi2s",
	[MT8189_CLK_TOP_TDMOUT_M_SEL] = "top_dptx",
	/* top 26m*/
	[MT8189_CLK_TOP_CLK26M] = "clk26m",
	/* peri */
	[MT8189_CLK_PERAO_AUDIO_SLV_CK_PERI] = "aud_slv_ck_peri",
	[MT8189_CLK_PERAO_AUDIO_MST_CK_PERI] = "aud_mst_ck_peri",
	[MT8189_CLK_PERAO_INTBUS_CK_PERI] = "aud_intbus_ck_peri",
};

int mt8189_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
{
	int ret;

	ret = clk_prepare_enable(clk);
	if (ret) {
		dev_err(afe->dev, "failed to enable clk\n");
		return ret;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(mt8189_afe_enable_clk);

void mt8189_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
{
	if (clk)
		clk_disable_unprepare(clk);
	else

Annotation

Implementation Notes