sound/soc/mediatek/mt8192/mt8192-afe-clk.h

File Facts

System

Linux kernel

Corpus path

sound/soc/mediatek/mt8192/mt8192-afe-clk.h

Extension

.h

Size

8368 bytes

Lines

245

Domain

Driver Families

Bucket

sound/soc

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct mtk_base_afe

Annotated Snippet

#ifndef _MT8192_AFE_CLOCK_CTRL_H_
#define _MT8192_AFE_CLOCK_CTRL_H_

#define AP_PLL_CON3 0x0014
#define APLL1_CON0 0x0318
#define APLL1_CON1 0x031c
#define APLL1_CON2 0x0320
#define APLL1_CON4 0x0328
#define APLL1_TUNER_CON0 0x0040

#define APLL2_CON0 0x032c
#define APLL2_CON1 0x0330
#define APLL2_CON2 0x0334
#define APLL2_CON4 0x033c
#define APLL2_TUNER_CON0 0x0044

#define CLK_CFG_7 0x0080
#define CLK_CFG_8 0x0090
#define CLK_CFG_11 0x00c0
#define CLK_CFG_12 0x00d0
#define CLK_CFG_13 0x00e0
#define CLK_CFG_15 0x0100

#define CLK_AUDDIV_0 0x0320
#define CLK_AUDDIV_2 0x0328
#define CLK_AUDDIV_3 0x0334
#define CLK_AUDDIV_4 0x0338
#define CKSYS_AUD_TOP_CFG 0x032c
#define CKSYS_AUD_TOP_MON 0x0330

#define PERI_BUS_DCM_CTRL 0x0074
#define MODULE_SW_CG_1_STA 0x0094
#define MODULE_SW_CG_2_STA 0x00ac

/* CLK_AUDDIV_0 */
#define APLL12_DIV0_PDN_SFT                0
#define APLL12_DIV0_PDN_MASK               0x1
#define APLL12_DIV0_PDN_MASK_SFT           (0x1 << 0)
#define APLL12_DIV1_PDN_SFT                1
#define APLL12_DIV1_PDN_MASK               0x1
#define APLL12_DIV1_PDN_MASK_SFT           (0x1 << 1)
#define APLL12_DIV2_PDN_SFT                2
#define APLL12_DIV2_PDN_MASK               0x1
#define APLL12_DIV2_PDN_MASK_SFT           (0x1 << 2)
#define APLL12_DIV3_PDN_SFT                3
#define APLL12_DIV3_PDN_MASK               0x1
#define APLL12_DIV3_PDN_MASK_SFT           (0x1 << 3)
#define APLL12_DIV4_PDN_SFT                4
#define APLL12_DIV4_PDN_MASK               0x1
#define APLL12_DIV4_PDN_MASK_SFT           (0x1 << 4)
#define APLL12_DIVB_PDN_SFT                5
#define APLL12_DIVB_PDN_MASK               0x1
#define APLL12_DIVB_PDN_MASK_SFT           (0x1 << 5)
#define APLL12_DIV5_PDN_SFT                6
#define APLL12_DIV5_PDN_MASK               0x1
#define APLL12_DIV5_PDN_MASK_SFT           (0x1 << 6)
#define APLL12_DIV6_PDN_SFT                7
#define APLL12_DIV6_PDN_MASK               0x1
#define APLL12_DIV6_PDN_MASK_SFT           (0x1 << 7)
#define APLL12_DIV7_PDN_SFT                8
#define APLL12_DIV7_PDN_MASK               0x1
#define APLL12_DIV7_PDN_MASK_SFT           (0x1 << 8)
#define APLL12_DIV8_PDN_SFT                9
#define APLL12_DIV8_PDN_MASK               0x1
#define APLL12_DIV8_PDN_MASK_SFT           (0x1 << 9)
#define APLL12_DIV9_PDN_SFT                10
#define APLL12_DIV9_PDN_MASK               0x1
#define APLL12_DIV9_PDN_MASK_SFT           (0x1 << 10)
#define APLL_I2S0_MCK_SEL_SFT              16
#define APLL_I2S0_MCK_SEL_MASK             0x1
#define APLL_I2S0_MCK_SEL_MASK_SFT         (0x1 << 16)
#define APLL_I2S1_MCK_SEL_SFT              17
#define APLL_I2S1_MCK_SEL_MASK             0x1
#define APLL_I2S1_MCK_SEL_MASK_SFT         (0x1 << 17)
#define APLL_I2S2_MCK_SEL_SFT              18
#define APLL_I2S2_MCK_SEL_MASK             0x1
#define APLL_I2S2_MCK_SEL_MASK_SFT         (0x1 << 18)
#define APLL_I2S3_MCK_SEL_SFT              19
#define APLL_I2S3_MCK_SEL_MASK             0x1
#define APLL_I2S3_MCK_SEL_MASK_SFT         (0x1 << 19)
#define APLL_I2S4_MCK_SEL_SFT              20
#define APLL_I2S4_MCK_SEL_MASK             0x1
#define APLL_I2S4_MCK_SEL_MASK_SFT         (0x1 << 20)
#define APLL_I2S5_MCK_SEL_SFT              21
#define APLL_I2S5_MCK_SEL_MASK             0x1
#define APLL_I2S5_MCK_SEL_MASK_SFT         (0x1 << 21)
#define APLL_I2S6_MCK_SEL_SFT              22
#define APLL_I2S6_MCK_SEL_MASK             0x1
#define APLL_I2S6_MCK_SEL_MASK_SFT         (0x1 << 22)
#define APLL_I2S7_MCK_SEL_SFT              23

Annotation

• Detected declarations: `struct mtk_base_afe`.
• Atlas domain: Driver Families / sound/soc.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.