sound/soc/mediatek/mt8192/mt8192-reg.h

Source file repositories/reference/linux-study-clean/sound/soc/mediatek/mt8192/mt8192-reg.h

File Facts

System
Linux kernel
Corpus path
sound/soc/mediatek/mt8192/mt8192-reg.h
Extension
.h
Size
181726 bytes
Lines
3134
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _MT8192_REG_H_
#define _MT8192_REG_H_

/* reg bit enum */
enum {
	MT8192_MEMIF_PBUF_SIZE_32_BYTES,
	MT8192_MEMIF_PBUF_SIZE_64_BYTES,
	MT8192_MEMIF_PBUF_SIZE_128_BYTES,
	MT8192_MEMIF_PBUF_SIZE_256_BYTES,
	MT8192_MEMIF_PBUF_SIZE_NUM,
};

/*****************************************************************************
 *                  R E G I S T E R       D E F I N I T I O N
 *****************************************************************************/
/* AUDIO_TOP_CON3 */
#define BCK_INVERSE_SFT                              3
#define BCK_INVERSE_MASK                             0x1
#define BCK_INVERSE_MASK_SFT                         (0x1 << 3)

/* AFE_DAC_CON0 */
#define VUL12_ON_SFT                                   31
#define VUL12_ON_MASK                                  0x1
#define VUL12_ON_MASK_SFT                              (0x1 << 31)
#define MOD_DAI_ON_SFT                                 30
#define MOD_DAI_ON_MASK                                0x1
#define MOD_DAI_ON_MASK_SFT                            (0x1 << 30)
#define DAI_ON_SFT                                     29
#define DAI_ON_MASK                                    0x1
#define DAI_ON_MASK_SFT                                (0x1 << 29)
#define DAI2_ON_SFT                                    28
#define DAI2_ON_MASK                                   0x1
#define DAI2_ON_MASK_SFT                               (0x1 << 28)
#define VUL6_ON_SFT                                    23
#define VUL6_ON_MASK                                   0x1
#define VUL6_ON_MASK_SFT                               (0x1 << 23)
#define VUL5_ON_SFT                                    22
#define VUL5_ON_MASK                                   0x1
#define VUL5_ON_MASK_SFT                               (0x1 << 22)
#define VUL4_ON_SFT                                    21
#define VUL4_ON_MASK                                   0x1
#define VUL4_ON_MASK_SFT                               (0x1 << 21)
#define VUL3_ON_SFT                                    20
#define VUL3_ON_MASK                                   0x1
#define VUL3_ON_MASK_SFT                               (0x1 << 20)
#define VUL2_ON_SFT                                    19
#define VUL2_ON_MASK                                   0x1
#define VUL2_ON_MASK_SFT                               (0x1 << 19)
#define VUL_ON_SFT                                     18
#define VUL_ON_MASK                                    0x1
#define VUL_ON_MASK_SFT                                (0x1 << 18)
#define AWB2_ON_SFT                                    17
#define AWB2_ON_MASK                                   0x1
#define AWB2_ON_MASK_SFT                               (0x1 << 17)
#define AWB_ON_SFT                                     16
#define AWB_ON_MASK                                    0x1
#define AWB_ON_MASK_SFT                                (0x1 << 16)
#define DL12_ON_SFT                                    15
#define DL12_ON_MASK                                   0x1
#define DL12_ON_MASK_SFT                               (0x1 << 15)
#define DL9_ON_SFT                                     12
#define DL9_ON_MASK                                    0x1
#define DL9_ON_MASK_SFT                                (0x1 << 12)
#define DL8_ON_SFT                                     11
#define DL8_ON_MASK                                    0x1
#define DL8_ON_MASK_SFT                                (0x1 << 11)
#define DL7_ON_SFT                                     10
#define DL7_ON_MASK                                    0x1
#define DL7_ON_MASK_SFT                                (0x1 << 10)
#define DL6_ON_SFT                                     9
#define DL6_ON_MASK                                    0x1
#define DL6_ON_MASK_SFT                                (0x1 << 9)
#define DL5_ON_SFT                                     8
#define DL5_ON_MASK                                    0x1
#define DL5_ON_MASK_SFT                                (0x1 << 8)
#define DL4_ON_SFT                                     7
#define DL4_ON_MASK                                    0x1
#define DL4_ON_MASK_SFT                                (0x1 << 7)
#define DL3_ON_SFT                                     6
#define DL3_ON_MASK                                    0x1
#define DL3_ON_MASK_SFT                                (0x1 << 6)
#define DL2_ON_SFT                                     5
#define DL2_ON_MASK                                    0x1
#define DL2_ON_MASK_SFT                                (0x1 << 5)
#define DL1_ON_SFT                                     4
#define DL1_ON_MASK                                    0x1
#define DL1_ON_MASK_SFT                                (0x1 << 4)
#define HDMI_OUT_ON_SFT                                1
#define HDMI_OUT_ON_MASK                               0x1
#define HDMI_OUT_ON_MASK_SFT                           (0x1 << 1)

Annotation

Implementation Notes