sound/soc/mediatek/mt8195/mt8195-afe-clk.c

File Facts

System

Linux kernel

Corpus path

sound/soc/mediatek/mt8195/mt8195-afe-clk.c

Extension

.c

Size

18152 bytes

Lines

711

Domain

Driver Families

Bucket

sound/soc

Inferred role

Driver Families: exported/initcall integration point

Status

integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/clk.h
• mt8195-afe-common.h
• mt8195-afe-clk.h
• mt8195-reg.h
• mt8195-audsys-clk.h

Detected Declarations

• struct mt8195_afe_tuner_cfg
• function mt8195_afe_init_apll_tuner
• function mt8195_afe_setup_apll_tuner
• function mt8195_afe_enable_tuner_clk
• function mt8195_afe_disable_tuner_clk
• function mt8195_afe_enable_apll_tuner
• function scoped_guard
• function mt8195_afe_disable_apll_tuner
• function scoped_guard
• function mt8195_afe_get_mclk_source_clk_id
• function mt8195_afe_get_mclk_source_rate
• function mt8195_afe_get_default_mclk_source_by_rate
• function mt8195_afe_init_clock
• function mt8195_afe_enable_clk
• function mt8195_afe_disable_clk
• function mt8195_afe_prepare_clk
• function mt8195_afe_unprepare_clk
• function mt8195_afe_enable_clk_atomic
• function mt8195_afe_disable_clk_atomic
• function mt8195_afe_set_clk_rate
• function mt8195_afe_set_clk_parent
• function get_top_cg_reg
• function get_top_cg_mask
• function get_top_cg_on_val
• function get_top_cg_off_val
• function mt8195_afe_enable_top_cg
• function mt8195_afe_disable_top_cg
• function mt8195_afe_enable_reg_rw_clk
• function mt8195_afe_disable_reg_rw_clk
• function mt8195_afe_enable_afe_on
• function mt8195_afe_disable_afe_on
• function mt8195_afe_enable_timing_sys
• function mt8195_afe_disable_timing_sys
• function mt8195_afe_enable_main_clock
• function mt8195_afe_disable_main_clock
• export mt8195_afe_enable_clk
• export mt8195_afe_disable_clk

Annotated Snippet

struct mt8195_afe_tuner_cfg {
	unsigned int id;
	int apll_div_reg;
	unsigned int apll_div_shift;
	unsigned int apll_div_maskbit;
	unsigned int apll_div_default;
	int ref_ck_sel_reg;
	unsigned int ref_ck_sel_shift;
	unsigned int ref_ck_sel_maskbit;
	unsigned int ref_ck_sel_default;
	int tuner_en_reg;
	unsigned int tuner_en_shift;
	unsigned int tuner_en_maskbit;
	int upper_bound_reg;
	unsigned int upper_bound_shift;
	unsigned int upper_bound_maskbit;
	unsigned int upper_bound_default;
	spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/
	int ref_cnt;
};

static struct mt8195_afe_tuner_cfg mt8195_afe_tuner_cfgs[MT8195_AUD_PLL_NUM] = {
	[MT8195_AUD_PLL1] = {
		.id = MT8195_AUD_PLL1,
		.apll_div_reg = AFE_APLL_TUNER_CFG,
		.apll_div_shift = 4,
		.apll_div_maskbit = 0xf,
		.apll_div_default = 0x7,
		.ref_ck_sel_reg = AFE_APLL_TUNER_CFG,
		.ref_ck_sel_shift = 1,
		.ref_ck_sel_maskbit = 0x3,
		.ref_ck_sel_default = 0x2,
		.tuner_en_reg = AFE_APLL_TUNER_CFG,
		.tuner_en_shift = 0,
		.tuner_en_maskbit = 0x1,
		.upper_bound_reg = AFE_APLL_TUNER_CFG,
		.upper_bound_shift = 8,
		.upper_bound_maskbit = 0xff,
		.upper_bound_default = 0x3,
	},
	[MT8195_AUD_PLL2] = {
		.id = MT8195_AUD_PLL2,
		.apll_div_reg = AFE_APLL_TUNER_CFG1,
		.apll_div_shift = 4,
		.apll_div_maskbit = 0xf,
		.apll_div_default = 0x7,
		.ref_ck_sel_reg = AFE_APLL_TUNER_CFG1,
		.ref_ck_sel_shift = 1,
		.ref_ck_sel_maskbit = 0x3,
		.ref_ck_sel_default = 0x1,
		.tuner_en_reg = AFE_APLL_TUNER_CFG1,
		.tuner_en_shift = 0,
		.tuner_en_maskbit = 0x1,
		.upper_bound_reg = AFE_APLL_TUNER_CFG1,
		.upper_bound_shift = 8,
		.upper_bound_maskbit = 0xff,
		.upper_bound_default = 0x3,
	},
	[MT8195_AUD_PLL3] = {
		.id = MT8195_AUD_PLL3,
		.apll_div_reg = AFE_EARC_APLL_TUNER_CFG,
		.apll_div_shift = 4,
		.apll_div_maskbit = 0x3f,
		.apll_div_default = 0x3,
		.ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG,
		.ref_ck_sel_shift = 24,
		.ref_ck_sel_maskbit = 0x3,
		.ref_ck_sel_default = 0x0,
		.tuner_en_reg = AFE_EARC_APLL_TUNER_CFG,
		.tuner_en_shift = 0,
		.tuner_en_maskbit = 0x1,
		.upper_bound_reg = AFE_EARC_APLL_TUNER_CFG,
		.upper_bound_shift = 12,
		.upper_bound_maskbit = 0xff,
		.upper_bound_default = 0x4,
	},
	[MT8195_AUD_PLL4] = {
		.id = MT8195_AUD_PLL4,
		.apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
		.apll_div_shift = 4,
		.apll_div_maskbit = 0x3f,
		.apll_div_default = 0x7,
		.ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1,
		.ref_ck_sel_shift = 8,
		.ref_ck_sel_maskbit = 0x1,
		.ref_ck_sel_default = 0,
		.tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
		.tuner_en_shift = 0,
		.tuner_en_maskbit = 0x1,
		.upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG,

Annotation

• Immediate include surface: `linux/clk.h`, `mt8195-afe-common.h`, `mt8195-afe-clk.h`, `mt8195-reg.h`, `mt8195-audsys-clk.h`.
• Detected declarations: `struct mt8195_afe_tuner_cfg`, `function mt8195_afe_init_apll_tuner`, `function mt8195_afe_setup_apll_tuner`, `function mt8195_afe_enable_tuner_clk`, `function mt8195_afe_disable_tuner_clk`, `function mt8195_afe_enable_apll_tuner`, `function scoped_guard`, `function mt8195_afe_disable_apll_tuner`, `function scoped_guard`, `function mt8195_afe_get_mclk_source_clk_id`.
• Atlas domain: Driver Families / sound/soc.
• Implementation status: integration implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.