sound/soc/mediatek/mt8195/mt8195-dai-adda.c

Source file repositories/reference/linux-study-clean/sound/soc/mediatek/mt8195/mt8195-dai-adda.c

File Facts

System
Linux kernel
Corpus path
sound/soc/mediatek/mt8195/mt8195-dai-adda.c
Extension
.c
Size
21507 bytes
Lines
754
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mtk_dai_adda_priv {
	bool hires_required;
};

static int mt8195_adda_mtkaif_init(struct mtk_base_afe *afe)
{
	struct mt8195_afe_private *afe_priv = afe->platform_priv;
	struct mtkaif_param *param = &afe_priv->mtkaif_params;
	int delay_data;
	int delay_cycle;
	unsigned int mask = 0;
	unsigned int val = 0;

	/* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */
	mask = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
	val = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);

	regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, mask, val);
	regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, mask, val);

	mask = RG_RX_PROTOCOL2;
	val = RG_RX_PROTOCOL2;
	regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, mask, val);

	if (!param->mtkaif_calibration_ok) {
		dev_info(afe->dev, "%s(), calibration fail\n",  __func__);
		return 0;
	}

	/* set delay for ch1, ch2 */
	if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] >=
	    param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
		delay_data = DELAY_DATA_MISO1;
		delay_cycle =
			param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] -
			param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
	} else {
		delay_data = DELAY_DATA_MISO0;
		delay_cycle =
			param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
			param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0];
	}

	val = 0;
	mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
	val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
	       MTKAIF_RXIF_DELAY_CYCLE_MASK;
	val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
	regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val);

	/* set delay between ch3 and ch2 */
	if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] >=
	    param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
		delay_data = DELAY_DATA_MISO1;
		delay_cycle =
			param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] -
			param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
	} else {
		delay_data = DELAY_DATA_MISO2;
		delay_cycle =
			param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
			param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2];
	}

	val = 0;
	mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
	val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
	       MTKAIF_RXIF_DELAY_CYCLE_MASK;
	val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
	regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_RX_CFG2, mask, val);

	return 0;
}

static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
				     struct snd_kcontrol *kcontrol,
				     int event)
{
	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);

	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
		__func__, w->name, event);

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		mt8195_adda_mtkaif_init(afe);
		break;
	default:
		break;

Annotation

Implementation Notes