sound/soc/mediatek/mt8195/mt8195-reg.h

Source file repositories/reference/linux-study-clean/sound/soc/mediatek/mt8195/mt8195-reg.h

File Facts

System: Linux kernel
Corpus path: sound/soc/mediatek/mt8195/mt8195-reg.h
Extension: .h
Size: 139606 bytes
Lines: 2798
Domain: Driver Families
Bucket: sound/soc
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _MT8195_REG_H_
#define _MT8195_REG_H_

#define AFE_SRAM_BASE                     (0x10880000)
#define AFE_SRAM_SIZE                     (0x10000)

#define AUDIO_TOP_CON0                    (0x0000)
#define AUDIO_TOP_CON1                    (0x0004)
#define AUDIO_TOP_CON2                    (0x0008)
#define AUDIO_TOP_CON3                    (0x000c)
#define AUDIO_TOP_CON4                    (0x0010)
#define AUDIO_TOP_CON5                    (0x0014)
#define AUDIO_TOP_CON6                    (0x0018)
#define AFE_MAS_HADDR_MSB                 (0x0020)
#define PWR1_ASM_CON1                     (0x0108)
#define ASYS_IRQ_CONFIG                   (0x0110)
#define ASYS_IRQ1_CON                     (0x0114)
#define ASYS_IRQ2_CON                     (0x0118)
#define ASYS_IRQ3_CON                     (0x011c)
#define ASYS_IRQ4_CON                     (0x0120)
#define ASYS_IRQ5_CON                     (0x0124)
#define ASYS_IRQ6_CON                     (0x0128)
#define ASYS_IRQ7_CON                     (0x012c)
#define ASYS_IRQ8_CON                     (0x0130)
#define ASYS_IRQ9_CON                     (0x0134)
#define ASYS_IRQ10_CON                    (0x0138)
#define ASYS_IRQ11_CON                    (0x013c)
#define ASYS_IRQ12_CON                    (0x0140)
#define ASYS_IRQ13_CON                    (0x0144)
#define ASYS_IRQ14_CON                    (0x0148)
#define ASYS_IRQ15_CON                    (0x014c)
#define ASYS_IRQ16_CON                    (0x0150)
#define ASYS_IRQ_CLR                      (0x0154)
#define ASYS_IRQ_STATUS                   (0x0158)
#define ASYS_IRQ_MON1                     (0x015c)
#define ASYS_IRQ_MON2                     (0x0160)
#define AFE_IRQ1_CON                      (0x0164)
#define AFE_IRQ2_CON                      (0x0168)
#define AFE_IRQ3_CON                      (0x016c)
#define AFE_IRQ_MCU_CLR                   (0x0170)
#define AFE_IRQ_STATUS                    (0x0174)
#define AFE_IRQ_MASK                      (0x0178)
#define ASYS_IRQ_MASK                     (0x017c)
#define AFE_IRQ3_CON_MON                  (0x01b0)
#define AFE_IRQ_MCU_MON2                  (0x01b4)
#define AFE_IRQ8_CON                      (0x01b8)
#define AFE_IRQ9_CON                      (0x01bc)
#define AFE_IRQ10_CON                     (0x01c0)
#define AFE_IRQ9_CON_MON                  (0x01c4)
#define ADSP_IRQ_MASK                     (0x01c8)
#define ADSP_IRQ_STATUS                   (0x01cc)
#define AFE_SINEGEN_CON0                  (0x01f0)
#define AFE_SINEGEN_CON1                  (0x01f4)
#define AFE_SINEGEN_CON2                  (0x01f8)
#define AFE_SINEGEN_CON3                  (0x01fc)
#define AFE_SPDIF_OUT_CON0                (0x0380)
#define AFE_TDMOUT_CONN0                  (0x0390)
#define PWR1_ASM_CON2                     (0x03b0)
#define PWR1_ASM_CON3                     (0x03b4)
#define PWR1_ASM_CON4                     (0x03b8)
#define AFE_APLL_TUNER_CFG                (0x03f8)
#define AFE_APLL_TUNER_CFG1               (0x03fc)
#define AUDIO_TOP_STA0                    (0x0400)
#define AUDIO_TOP_STA1                    (0x0404)
#define AFE_GAIN1_CON0                    (0x0410)
#define AFE_GAIN1_CON1                    (0x0414)
#define AFE_GAIN1_CON2                    (0x0418)
#define AFE_GAIN1_CON3                    (0x041c)
#define AFE_GAIN1_CUR                     (0x0424)
#define AFE_GAIN2_CON0                    (0x0428)
#define AFE_GAIN2_CON1                    (0x042c)
#define AFE_GAIN2_CON2                    (0x0430)
#define AFE_GAIN2_CON3                    (0x0434)
#define AFE_GAIN2_CUR                     (0x043c)
#define AFE_IEC_CFG                       (0x0480)
#define AFE_IEC_NSNUM                     (0x0484)
#define AFE_IEC_BURST_INFO                (0x0488)
#define AFE_IEC_BURST_LEN                 (0x048c)
#define AFE_IEC_NSADR                     (0x0490)
#define AFE_IEC_CHL_STAT0                 (0x04a0)
#define AFE_IEC_CHL_STAT1                 (0x04a4)
#define AFE_IEC_CHR_STAT0                 (0x04a8)
#define AFE_IEC_CHR_STAT1                 (0x04ac)
#define AFE_SPDIFIN_CFG0                  (0x0500)
#define AFE_SPDIFIN_CFG1                  (0x0504)
#define AFE_SPDIFIN_CHSTS1                (0x0508)
#define AFE_SPDIFIN_CHSTS2                (0x050c)
#define AFE_SPDIFIN_CHSTS3                (0x0510)
#define AFE_SPDIFIN_CHSTS4                (0x0514)
#define AFE_SPDIFIN_CHSTS5                (0x0518)

Annotation

Atlas domain: Driver Families / sound/soc.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.