sound/soc/mediatek/mt8196/mt8196-afe-clk.h

File Facts

System

Linux kernel

Corpus path

sound/soc/mediatek/mt8196/mt8196-afe-clk.h

Extension

.h

Size

1957 bytes

Lines

65

Domain

Driver Families

Bucket

sound/soc

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct mtk_base_afe

Annotated Snippet

#ifndef _MT8196_AFE_CLOCK_CTRL_H_
#define _MT8196_AFE_CLOCK_CTRL_H_

#define MT8196_AFE_26M 26000000
#define MT8196_AUD_ENG1_CLK 45158400
#define MT8196_AUD_ENG2_CLK 49152000

/* APLL */
#define APLL1_W_NAME "APLL1"
#define APLL2_W_NAME "APLL2"

enum {
	MT8196_APLL1 = 0,
	MT8196_APLL2,
};

enum {
	/* vlp clk */
	MT8196_CLK_VLP_MUX_AUDIOINTBUS,
	MT8196_CLK_VLP_MUX_AUD_ENG1,
	MT8196_CLK_VLP_MUX_AUD_ENG2,
	MT8196_CLK_VLP_MUX_AUDIO_H,
	/* pll */
	MT8196_CLK_TOP_APLL1_CK,
	MT8196_CLK_TOP_APLL2_CK,
	/* divider */
	MT8196_CLK_TOP_APLL12_DIV_I2SIN0,
	MT8196_CLK_TOP_APLL12_DIV_I2SIN1,
	MT8196_CLK_TOP_APLL12_DIV_FMI2S,
	MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M,
	MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B,
	/* mux */
	MT8196_CLK_TOP_ADSP_SEL,
	MT8196_CLK_NUM,
};

struct mtk_base_afe;

int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id);
int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll);
int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
int mt8196_init_clock(struct mtk_base_afe *afe);
int mt8196_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
void mt8196_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
int mt8196_apll1_enable(struct mtk_base_afe *afe);
void mt8196_apll1_disable(struct mtk_base_afe *afe);
int mt8196_apll2_enable(struct mtk_base_afe *afe);
void mt8196_apll2_disable(struct mtk_base_afe *afe);
int mt8196_afe_enable_main_clock(struct mtk_base_afe *afe);
int mt8196_afe_disable_main_clock(struct mtk_base_afe *afe);
int mt8196_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
int mt8196_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);

#endif

Annotation

• Detected declarations: `struct mtk_base_afe`.
• Atlas domain: Driver Families / sound/soc.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.