sound/soc/mediatek/mt8196/mt8196-dai-adda.c

Source file repositories/reference/linux-study-clean/sound/soc/mediatek/mt8196/mt8196-dai-adda.c

File Facts

System
Linux kernel
Corpus path
sound/soc/mediatek/mt8196/mt8196-dai-adda.c
Extension
.c
Size
25190 bytes
Lines
846
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mtk_afe_adda_priv {
	int dl_rate;
	int ul_rate;
};

static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
					   unsigned int rate)
{
	switch (rate) {
	case 8000:
		return MTK_AFE_ADDA_UL_RATE_8K;
	case 16000:
		return MTK_AFE_ADDA_UL_RATE_16K;
	case 32000:
		return MTK_AFE_ADDA_UL_RATE_32K;
	case 48000:
		return MTK_AFE_ADDA_UL_RATE_48K;
	case 96000:
		return MTK_AFE_ADDA_UL_RATE_96K;
	case 192000:
		return MTK_AFE_ADDA_UL_RATE_192K;
	default:
		dev_warn(afe->dev, "rate %d invalid, use 48kHz!!!\n", rate);
		return MTK_AFE_ADDA_UL_RATE_48K;
	}
}

static unsigned int mtkaif_rate_transform(struct mtk_base_afe *afe,
					  unsigned int rate)
{
	switch (rate) {
	case 8000:
		return MTK_AFE_MTKAIF_RATE_8K;
	case 11025:
		return MTK_AFE_MTKAIF_RATE_11K;
	case 12000:
		return MTK_AFE_MTKAIF_RATE_12K;
	case 16000:
		return MTK_AFE_MTKAIF_RATE_16K;
	case 22050:
		return MTK_AFE_MTKAIF_RATE_22K;
	case 24000:
		return MTK_AFE_MTKAIF_RATE_24K;
	case 32000:
		return MTK_AFE_MTKAIF_RATE_32K;
	case 44100:
		return MTK_AFE_MTKAIF_RATE_44K;
	case 48000:
		return MTK_AFE_MTKAIF_RATE_48K;
	case 96000:
		return MTK_AFE_MTKAIF_RATE_96K;
	case 192000:
		return MTK_AFE_MTKAIF_RATE_192K;
	default:
		dev_warn(afe->dev, "rate %d invalid, use 48kHz!!!\n", rate);
		return MTK_AFE_MTKAIF_RATE_48K;
	}
}

enum {
	SUPPLY_SEQ_ADDA_AFE_ON,
	SUPPLY_SEQ_ADDA_FIFO,
	SUPPLY_SEQ_ADDA_AP_DMIC,
	SUPPLY_SEQ_ADDA_UL_ON,
};

static int mtk_adda_ul_src_set_dmic_phase_sync(struct mtk_base_afe *afe)
{
	dev_dbg(afe->dev, "set dmic phase sync\n");
	// ul0~1
	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
			   UL0_PHASE_SYNC_HCLK_SET_MASK_SFT,
			   0x1 << UL0_PHASE_SYNC_HCLK_SET_SFT);
	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
			   UL0_PHASE_SYNC_FCLK_SET_MASK_SFT,
			   0x1 << UL0_PHASE_SYNC_FCLK_SET_SFT);
	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
			   UL1_PHASE_SYNC_HCLK_SET_MASK_SFT,
			   0x1 << UL1_PHASE_SYNC_HCLK_SET_SFT);
	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
			   UL1_PHASE_SYNC_FCLK_SET_MASK_SFT,
			   0x1 << UL1_PHASE_SYNC_FCLK_SET_SFT);
	// dmic 0
	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
			   DMIC0_PHASE_SYNC_FCLK_SET_MASK_SFT,
			   0x1 << DMIC0_PHASE_SYNC_FCLK_SET_SFT);
	regmap_update_bits(afe->regmap, AFE_ADDA_ULSRC_PHASE_CON1,
			   DMIC0_PHASE_SYNC_HCLK_SET_MASK_SFT,
			   0x1 << DMIC0_PHASE_SYNC_HCLK_SET_SFT);
	// dmic 1

Annotation

Implementation Notes