sound/soc/rockchip/rockchip_sai.h

Source file repositories/reference/linux-study-clean/sound/soc/rockchip/rockchip_sai.h

File Facts

System
Linux kernel
Corpus path
sound/soc/rockchip/rockchip_sai.h
Extension
.h
Size
8141 bytes
Lines
252
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ROCKCHIP_SAI_H
#define _ROCKCHIP_SAI_H

/* XCR Transmit / Receive Control Register */
#define SAI_XCR_START_SEL_MASK		BIT(23)
#define SAI_XCR_START_SEL_CHAINED	BIT(23)
#define SAI_XCR_START_SEL_STANDALONE	0
#define SAI_XCR_EDGE_SHIFT_MASK		BIT(22)
#define SAI_XCR_EDGE_SHIFT_1		BIT(22)
#define SAI_XCR_EDGE_SHIFT_0		0
#define SAI_XCR_CSR_MASK		GENMASK(21, 20)
#define SAI_XCR_CSR(x)			((x - 1) << 20)
#define SAI_XCR_CSR_V(v)		((((v) & SAI_XCR_CSR_MASK) >> 20) + 1)
#define SAI_XCR_SJM_MASK		BIT(19)
#define SAI_XCR_SJM_L			BIT(19)
#define SAI_XCR_SJM_R			0
#define SAI_XCR_FBM_MASK		BIT(18)
#define SAI_XCR_FBM_LSB			BIT(18)
#define SAI_XCR_FBM_MSB			0
#define SAI_XCR_SNB_MASK		GENMASK(17, 11)
#define SAI_XCR_SNB(x)			((x - 1) << 11)
#define SAI_XCR_VDJ_MASK		BIT(10)
#define SAI_XCR_VDJ_L			BIT(10)
#define SAI_XCR_VDJ_R			0
#define SAI_XCR_SBW_MASK		GENMASK(9, 5)
#define SAI_XCR_SBW(x)			((x - 1) << 5)
#define SAI_XCR_SBW_V(v)		((((v) & SAI_XCR_SBW_MASK) >> 5) + 1)
#define SAI_XCR_VDW_MASK		GENMASK(4, 0)
#define SAI_XCR_VDW(x)			((x - 1) << 0)

/* FSCR Frame Sync Control Register */
#define SAI_FSCR_EDGE_MASK		BIT(24)
#define SAI_FSCR_EDGE_DUAL		BIT(24)
#define SAI_FSCR_EDGE_RISING		0
#define SAI_FSCR_FPW_MASK		GENMASK(23, 12)
#define SAI_FSCR_FPW(x)			((x - 1) << 12)
#define SAI_FSCR_FW_MASK		GENMASK(11, 0)
#define SAI_FSCR_FW(x)			((x - 1) << 0)
#define SAI_FSCR_FW_V(v)		((((v) & SAI_FSCR_FW_MASK) >> 0) + 1)

/* MONO_CR Mono Control Register */
#define SAI_MCR_RX_MONO_SLOT_MASK	GENMASK(8, 2)
#define SAI_MCR_RX_MONO_SLOT_SEL(x)	((x - 1) << 2)
#define SAI_MCR_RX_MONO_MASK		BIT(1)
#define SAI_MCR_RX_MONO_EN		BIT(1)
#define SAI_MCR_RX_MONO_DIS		0
#define SAI_MCR_TX_MONO_MASK		BIT(0)
#define SAI_MCR_TX_MONO_EN		BIT(0)
#define SAI_MCR_TX_MONO_DIS		0

/* XFER Transfer Start Register */
#define SAI_XFER_RX_IDLE		BIT(8)
#define SAI_XFER_TX_IDLE		BIT(7)
#define SAI_XFER_FS_IDLE		BIT(6)
/*
 * Used for TX only (VERSION >= SAI_VER_2311)
 *
 * SCLK/FSYNC auto gated when TX FIFO empty.
 */
#define SAI_XFER_TX_AUTO_MASK		BIT(6)
#define SAI_XFER_TX_AUTO_EN		BIT(6)
#define SAI_XFER_TX_AUTO_DIS		0
#define SAI_XFER_RX_CNT_MASK		BIT(5)
#define SAI_XFER_RX_CNT_EN		BIT(5)
#define SAI_XFER_RX_CNT_DIS		0
#define SAI_XFER_TX_CNT_MASK		BIT(4)
#define SAI_XFER_TX_CNT_EN		BIT(4)
#define SAI_XFER_TX_CNT_DIS		0
#define SAI_XFER_RXS_MASK		BIT(3)
#define SAI_XFER_RXS_EN			BIT(3)
#define SAI_XFER_RXS_DIS		0
#define SAI_XFER_TXS_MASK		BIT(2)
#define SAI_XFER_TXS_EN			BIT(2)
#define SAI_XFER_TXS_DIS		0
#define SAI_XFER_FSS_MASK		BIT(1)
#define SAI_XFER_FSS_EN			BIT(1)
#define SAI_XFER_FSS_DIS		0
#define SAI_XFER_CLK_MASK		BIT(0)
#define SAI_XFER_CLK_EN			BIT(0)
#define SAI_XFER_CLK_DIS		0

/* CLR Clear Logic Register */
#define SAI_CLR_FCR			BIT(3)	/* TODO: what is this? */
#define SAI_CLR_FSC			BIT(2)
#define SAI_CLR_RXC			BIT(1)
#define SAI_CLR_TXC			BIT(0)

/* CKR Clock Generation Register */
#define SAI_CKR_MDIV_MASK		GENMASK(14, 3)
#define SAI_CKR_MDIV(x)			((x - 1) << 3)

Annotation

Implementation Notes