sound/soc/rockchip/rockchip_spdif.h

Source file repositories/reference/linux-study-clean/sound/soc/rockchip/rockchip_spdif.h

File Facts

System
Linux kernel
Corpus path
sound/soc/rockchip/rockchip_spdif.h
Extension
.h
Size
2297 bytes
Lines
74
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ROCKCHIP_SPDIF_H
#define _ROCKCHIP_SPDIF_H

/*
 * CFGR
 * transfer configuration register
*/
#define SPDIF_CFGR_CLK_DIV_MASK		GENMASK(23, 16)
#define SPDIF_CFGR_CLK_DIV(x)		FIELD_PREP(SPDIF_CFGR_CLK_DIV_MASK, x-1)

#define SPDIF_CFGR_CLR_MASK		BIT(7)
#define SPDIF_CFGR_CLR_EN		FIELD_PREP(SPDIF_CFGR_CLR_MASK, 1)
#define SPDIF_CFGR_CLR_DIS		FIELD_PREP(SPDIF_CFGR_CLR_MASK, 0)

#define SPDIF_CFGR_CSE_MASK		BIT(6)
#define SPDIF_CFGR_CSE_EN		FIELD_PREP(SPDIF_CFGR_CSE_MASK, 1)
#define SPDIF_CFGR_CSE_DIS		FIELD_PREP(SPDIF_CFGR_CSE_MASK, 0)

#define SPDIF_CFGR_ADJ_MASK		BIT(3)
#define SPDIF_CFGR_ADJ_LEFT_J		FIELD_PREP(SPDIF_CFGR_ADJ_MASK, 1)
#define SPDIF_CFGR_ADJ_RIGHT_J		FIELD_PREP(SPDIF_CFGR_ADJ_MASK, 0)

#define SPDIF_CFGR_HALFWORD_MASK	BIT(2)
#define SPDIF_CFGR_HALFWORD_DISABLE	FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 0)
#define SPDIF_CFGR_HALFWORD_ENABLE	FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 1)

#define SDPIF_CFGR_VDW_MASK		GENMASK(1, 0)
#define SPDIF_CFGR_VDW(x)		FIELD_PREP(SDPIF_CFGR_VDW_MASK, x)

#define SPDIF_CFGR_VDW_16		SPDIF_CFGR_VDW(0x0)
#define SPDIF_CFGR_VDW_20		SPDIF_CFGR_VDW(0x1)
#define SPDIF_CFGR_VDW_24		SPDIF_CFGR_VDW(0x2)

/*
 * DMACR
 * DMA control register
*/
#define SPDIF_DMACR_TDE_MASK		BIT(5)
#define SPDIF_DMACR_TDE_DISABLE		FIELD_PREP(SPDIF_DMACR_TDE_MASK, 0)
#define SPDIF_DMACR_TDE_ENABLE		FIELD_PREP(SPDIF_DMACR_TDE_MASK, 1)

#define SPDIF_DMACR_TDL_MASK		GENMASK(4, 0)
#define SPDIF_DMACR_TDL(x)		FIELD_PREP(SPDIF_DMACR_TDL_MASK, x)

/*
 * XFER
 * Transfer control register
*/
#define SPDIF_XFER_TXS_MASK		BIT(0)
#define SPDIF_XFER_TXS_STOP		FIELD_PREP(SPDIF_XFER_TXS_MASK, 0)
#define SPDIF_XFER_TXS_START		FIELD_PREP(SPDIF_XFER_TXS_MASK, 1)

#define SPDIF_CFGR	(0x0000)
#define SPDIF_SDBLR	(0x0004)
#define SPDIF_DMACR	(0x0008)
#define SPDIF_INTCR	(0x000c)
#define SPDIF_INTSR	(0x0010)
#define SPDIF_XFER	(0x0018)
#define SPDIF_SMPDR	(0x0020)
#define SPDIF_VLDFRn(x)	(0x0060 + (x) * 4)
#define SPDIF_USRDRn(x)	(0x0090 + (x) * 4)
#define SPDIF_CHNSRn(x)	(0x00c0 + (x) * 4)
#define SPDIF_VERSION	(0x01c0)

#endif /* _ROCKCHIP_SPDIF_H */

Annotation

Implementation Notes