sound/soc/sof/intel/hda.h

Source file repositories/reference/linux-study-clean/sound/soc/sof/intel/hda.h

File Facts

System
Linux kernel
Corpus path
sound/soc/sof/intel/hda.h
Extension
.h
Size
36884 bytes
Lines
1069
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sof_intel_dsp_bdl {
	__le32 addr_l;
	__le32 addr_h;
	__le32 size;
	__le32 ioc;
} __attribute((packed));

#define SOF_HDA_PLAYBACK_STREAMS	16
#define SOF_HDA_CAPTURE_STREAMS		16
#define SOF_HDA_PLAYBACK		0
#define SOF_HDA_CAPTURE			1

/* stream flags */
#define SOF_HDA_STREAM_DMI_L1_COMPATIBLE	1

/*
 * Time in ms for opportunistic D0I3 entry delay.
 * This has been deliberately chosen to be long to avoid race conditions.
 * Could be optimized in future.
 */
#define SOF_HDA_D0I3_WORK_DELAY_MS	5000

/* HDA DSP D0 substate */
enum sof_hda_D0_substate {
	SOF_HDA_DSP_PM_D0I0,	/* default D0 substate */
	SOF_HDA_DSP_PM_D0I3,	/* low power D0 substate */
};

struct sof_ace3_mic_privacy {
	bool active;
	struct work_struct work;
};

/* represents DSP HDA controller frontend - i.e. host facing control */
struct sof_intel_hda_dev {
	bool imrboot_supported;
	bool skip_imr_boot;
	bool booted_from_imr;

	int boot_iteration;

	/*
	 * DMA buffers for base firmware download. By default the buffers are
	 * allocated once and kept through the lifetime of the driver.
	 * See module parameter: persistent_cl_buffer
	 */
	struct snd_dma_buffer cl_dmab;
	bool cl_dmab_contains_basefw;
	struct snd_dma_buffer iccmax_dmab;

	struct hda_bus hbus;

	/* hw config */
	const struct sof_intel_dsp_desc *desc;

	/* trace */
	struct hdac_ext_stream *dtrace_stream;

	/* if position update IPC needed */
	u32 no_ipc_position;

	/* the maximum number of streams (playback + capture) supported */
	u32 stream_max;

	/* PM related */
	bool l1_disabled;/* is DMI link L1 disabled? */

	/* DMIC device */
	struct platform_device *dmic_dev;

	/* delayed work to enter D0I3 opportunistically */
	struct delayed_work d0i3_work;

	/* ACPI information stored between scan and probe steps */
	struct sdw_intel_acpi_info info;

	/* sdw context allocated by SoundWire driver */
	struct sdw_intel_ctx *sdw;

	/* FW clock config, 0:HPRO, 1:LPRO */
	bool clk_config_lpro;

	wait_queue_head_t waitq;
	bool code_loading;

	/* Intel NHLT information */
	struct nhlt_acpi_table *nhlt;

	/* work queue for mic privacy state change notification sending */
	struct sof_ace3_mic_privacy mic_privacy;

Annotation

Implementation Notes