sound/soc/sof/intel/hda-loader-skl.c

Source file repositories/reference/linux-study-clean/sound/soc/sof/intel/hda-loader-skl.c

File Facts

System
Linux kernel
Corpus path
sound/soc/sof/intel/hda-loader-skl.c
Extension
.c
Size
16695 bytes
Lines
579
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (ret < 0) {
			dev_err(sdev->dev, "%s: dsp core start failed %d\n", __func__, ret);
			goto err;
		}
	} else {
		/* if not enabled, power down it first and then powerup and run
		 * the init_core.
		 */
		ret = hda_dsp_core_reset_power_down(sdev, chip->init_core_mask);
		if (ret < 0) {
			dev_err(sdev->dev, "%s: dsp core0 disable fail: %d\n", __func__, ret);
			goto err;
		}
		ret = hda_dsp_enable_core(sdev, chip->init_core_mask);
		if (ret < 0) {
			dev_err(sdev->dev, "%s: dsp core0 enable fail: %d\n", __func__, ret);
			goto err;
		}
	}

	/* prepare DMA for code loader stream */
	ret = cl_stream_prepare_skl(sdev, dmab, dmab_bdl);
	if (ret < 0) {
		dev_err(sdev->dev, "%s: dma prepare fw loading err: %x\n", __func__, ret);
		return ret;
	}

	/* enable the interrupt */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
				HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);

	/* enable IPC DONE interrupt */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
				HDA_DSP_REG_HIPCCTL_DONE,
				HDA_DSP_REG_HIPCCTL_DONE);

	/* enable IPC BUSY interrupt */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
				HDA_DSP_REG_HIPCCTL_BUSY,
				HDA_DSP_REG_HIPCCTL_BUSY);

	/* polling the ROM init status information. */
	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
					    chip->rom_status_reg, status,
					    (FSR_TO_STATE_CODE(status)
					     == FSR_STATE_INIT_DONE),
					    HDA_DSP_REG_POLL_INTERVAL_US,
					    chip->rom_init_timeout *
					    USEC_PER_MSEC);
	if (ret < 0)
		goto err;

	return ret;

err:
	flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX;

	snd_sof_dsp_dbg_dump(sdev, "Boot failed\n", flags);
	cl_cleanup_skl(sdev, dmab, dmab_bdl);
	hda_dsp_core_reset_power_down(sdev, chip->init_core_mask);
	return ret;
}

static void cl_skl_cldma_fill_buffer(struct snd_sof_dev *sdev,
				     struct snd_dma_buffer *dmab,
				     unsigned int bufsize,
				     unsigned int copysize,
				     const void *curr_pos,
				     bool intr_enable)
{
	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;

	/* copy the image into the buffer with the maximum buffer size. */
	unsigned int size = (bufsize == copysize) ? bufsize : copysize;

	memcpy(dmab->area, curr_pos, size);

	/* Set the wait condition for every load. */
	hda->code_loading = 1;

	/* Set the interrupt. */
	if (intr_enable)
		cl_skl_cldma_set_intr(sdev, true);

	/* Set the SPB. */
	cl_skl_cldma_setup_spb(sdev, size, true);

	/* Trigger the code loading stream. */
	cl_skl_cldma_stream_run(sdev, true);
}

Annotation

Implementation Notes