sound/soc/sof/xtensa/core.c
Source file repositories/reference/linux-study-clean/sound/soc/sof/xtensa/core.c
File Facts
- System
- Linux kernel
- Corpus path
sound/soc/sof/xtensa/core.c- Extension
.c- Size
- 5823 bytes
- Lines
- 156
- Domain
- Driver Families
- Bucket
- sound/soc
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hsound/sof.hsound/sof/xtensa.h../sof-priv.h
Detected Declarations
struct xtensa_exception_causefunction xtensa_dsp_oopsfunction xtensa_stack
Annotated Snippet
struct xtensa_exception_cause {
u32 id;
const char *msg;
const char *description;
};
/*
* From 4.4.1.5 table 4-64 Exception Causes of Xtensa
* Instruction Set Architecture (ISA) Reference Manual
*/
static const struct xtensa_exception_cause xtensa_exception_causes[] = {
{0, "IllegalInstructionCause", "Illegal instruction"},
{1, "SyscallCause", "SYSCALL instruction"},
{2, "InstructionFetchErrorCause",
"Processor internal physical address or data error during instruction fetch"},
{3, "LoadStoreErrorCause",
"Processor internal physical address or data error during load or store"},
{4, "Level1InterruptCause",
"Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"},
{5, "AllocaCause",
"MOVSP instruction, if caller’s registers are not in the register file"},
{6, "IntegerDivideByZeroCause",
"QUOS, QUOU, REMS, or REMU divisor operand is zero"},
{8, "PrivilegedCause",
"Attempt to execute a privileged operation when CRING ? 0"},
{9, "LoadStoreAlignmentCause", "Load or store to an unaligned address"},
{12, "InstrPIFDataErrorCause",
"PIF data error during instruction fetch"},
{13, "LoadStorePIFDataErrorCause",
"Synchronous PIF data error during LoadStore access"},
{14, "InstrPIFAddrErrorCause",
"PIF address error during instruction fetch"},
{15, "LoadStorePIFAddrErrorCause",
"Synchronous PIF address error during LoadStore access"},
{16, "InstTLBMissCause", "Error during Instruction TLB refill"},
{17, "InstTLBMultiHitCause",
"Multiple instruction TLB entries matched"},
{18, "InstFetchPrivilegeCause",
"An instruction fetch referenced a virtual address at a ring level less than CRING"},
{20, "InstFetchProhibitedCause",
"An instruction fetch referenced a page mapped with an attribute that does not permit instruction fetch"},
{24, "LoadStoreTLBMissCause",
"Error during TLB refill for a load or store"},
{25, "LoadStoreTLBMultiHitCause",
"Multiple TLB entries matched for a load or store"},
{26, "LoadStorePrivilegeCause",
"A load or store referenced a virtual address at a ring level less than CRING"},
{28, "LoadProhibitedCause",
"A load referenced a page mapped with an attribute that does not permit loads"},
{32, "Coprocessor0Disabled",
"Coprocessor 0 instruction when cp0 disabled"},
{33, "Coprocessor1Disabled",
"Coprocessor 1 instruction when cp1 disabled"},
{34, "Coprocessor2Disabled",
"Coprocessor 2 instruction when cp2 disabled"},
{35, "Coprocessor3Disabled",
"Coprocessor 3 instruction when cp3 disabled"},
{36, "Coprocessor4Disabled",
"Coprocessor 4 instruction when cp4 disabled"},
{37, "Coprocessor5Disabled",
"Coprocessor 5 instruction when cp5 disabled"},
{38, "Coprocessor6Disabled",
"Coprocessor 6 instruction when cp6 disabled"},
{39, "Coprocessor7Disabled",
"Coprocessor 7 instruction when cp7 disabled"},
};
/* only need xtensa atm */
static void xtensa_dsp_oops(struct snd_sof_dev *sdev, const char *level, void *oops)
{
struct sof_ipc_dsp_oops_xtensa *xoops = oops;
int i;
dev_printk(level, sdev->dev, "error: DSP Firmware Oops\n");
for (i = 0; i < ARRAY_SIZE(xtensa_exception_causes); i++) {
if (xtensa_exception_causes[i].id == xoops->exccause) {
dev_printk(level, sdev->dev,
"error: Exception Cause: %s, %s\n",
xtensa_exception_causes[i].msg,
xtensa_exception_causes[i].description);
}
}
dev_printk(level, sdev->dev,
"EXCCAUSE 0x%8.8x EXCVADDR 0x%8.8x PS 0x%8.8x SAR 0x%8.8x\n",
xoops->exccause, xoops->excvaddr, xoops->ps, xoops->sar);
dev_printk(level, sdev->dev,
"EPC1 0x%8.8x EPC2 0x%8.8x EPC3 0x%8.8x EPC4 0x%8.8x",
xoops->epc1, xoops->epc2, xoops->epc3, xoops->epc4);
dev_printk(level, sdev->dev,
"EPC5 0x%8.8x EPC6 0x%8.8x EPC7 0x%8.8x DEPC 0x%8.8x",
Annotation
- Immediate include surface: `linux/module.h`, `sound/sof.h`, `sound/sof/xtensa.h`, `../sof-priv.h`.
- Detected declarations: `struct xtensa_exception_cause`, `function xtensa_dsp_oops`, `function xtensa_stack`.
- Atlas domain: Driver Families / sound/soc.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.