sound/soc/tegra/tegra210_dmic.c

Source file repositories/reference/linux-study-clean/sound/soc/tegra/tegra210_dmic.c

File Facts

System
Linux kernel
Corpus path
sound/soc/tegra/tegra210_dmic.c
Extension
.c
Size
15872 bytes
Lines
569
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES.
// All rights reserved.
//
// tegra210_dmic.c - Tegra210 DMIC driver

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/math64.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_dmic.h"
#include "tegra_cif.h"

static const struct reg_default tegra210_dmic_reg_defaults[] = {
	{ TEGRA210_DMIC_TX_INT_MASK, 0x00000001 },
	{ TEGRA210_DMIC_TX_CIF_CTRL, 0x00007700 },
	{ TEGRA210_DMIC_CG, 0x1 },
	{ TEGRA210_DMIC_CTRL, 0x00000301 },
	/* Below enables all filters - DCR, LP and SC */
	{ TEGRA210_DMIC_DBG_CTRL, 0xe },
	/* Below as per latest POR value */
	{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4, 0x0 },
	/* LP filter is configured for pass through and used to apply gain */
	{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_0, 0x00800000 },
	{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_1, 0x0 },
	{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_2, 0x0 },
	{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_3, 0x0 },
	{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_4, 0x0 },
	{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_0, 0x00800000 },
	{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_1, 0x0 },
	{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_2, 0x0 },
	{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_3, 0x0 },
	{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_4, 0x0 },
};

static int tegra210_dmic_runtime_suspend(struct device *dev)
{
	struct tegra210_dmic *dmic = dev_get_drvdata(dev);

	regcache_cache_only(dmic->regmap, true);
	regcache_mark_dirty(dmic->regmap);

	clk_disable_unprepare(dmic->clk_dmic);

	return 0;
}

static int tegra210_dmic_runtime_resume(struct device *dev)
{
	struct tegra210_dmic *dmic = dev_get_drvdata(dev);
	int err;

	err = clk_prepare_enable(dmic->clk_dmic);
	if (err) {
		dev_err(dev, "failed to enable DMIC clock, err: %d\n", err);
		return err;
	}

	regcache_cache_only(dmic->regmap, false);
	regcache_sync(dmic->regmap);

	return 0;
}

static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream,
				   struct snd_pcm_hw_params *params,
				   struct snd_soc_dai *dai)
{
	struct tegra210_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	unsigned int srate, clk_rate, channels;
	struct tegra_cif_conf cif_conf;
	unsigned long long gain_q23 = DEFAULT_GAIN_Q23;
	int err;

	memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));

	channels = params_channels(params);

	cif_conf.audio_ch = channels;

	switch (dmic->ch_select) {
	case DMIC_CH_SELECT_LEFT:
	case DMIC_CH_SELECT_RIGHT:

Annotation

Implementation Notes