sound/soc/tegra/tegra210_mbdrc.c

Source file repositories/reference/linux-study-clean/sound/soc/tegra/tegra210_mbdrc.c

File Facts

System
Linux kernel
Corpus path
sound/soc/tegra/tegra210_mbdrc.c
Extension
.c
Size
31815 bytes
Lines
1021
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_mbdrc.c - Tegra210 MBDRC driver
//
// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.

#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/tlv.h>

#include "tegra210_mbdrc.h"
#include "tegra210_ope.h"

#define MBDRC_FILTER_REG(reg, id)					    \
	((reg) + ((id) * TEGRA210_MBDRC_FILTER_PARAM_STRIDE))

#define MBDRC_FILTER_REG_DEFAULTS(id)					    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IIR_CFG, id), 0x00000005},	    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_ATTACK, id), 0x3e48590c},	    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_RELEASE, id), 0x08414e9f},	    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_FAST_ATTACK, id), 0x7fffffff},    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_THRESHOLD, id), 0x06145082},   \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_OUT_THRESHOLD, id), 0x060d379b},  \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_1ST, id), 0x0000a000},	    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_2ND, id), 0x00002000},	    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_3RD, id), 0x00000b33},	    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_4TH, id), 0x00000800},	    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_5TH, id), 0x0000019a},	    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_MAKEUP_GAIN, id), 0x00000002},    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_INIT_GAIN, id), 0x00066666},	    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_GAIN_ATTACK, id), 0x00d9ba0e},    \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_GAIN_RELEASE, id), 0x3e48590c},   \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_FAST_RELEASE, id), 0x7ffff26a},   \
	{ MBDRC_FILTER_REG(TEGRA210_MBDRC_CFG_RAM_CTRL, id), 0x4000}

static const struct reg_default tegra210_mbdrc_reg_defaults[] = {
	{ TEGRA210_MBDRC_CFG, 0x0030de51},
	{ TEGRA210_MBDRC_CHANNEL_MASK, 0x00000003},
	{ TEGRA210_MBDRC_FAST_FACTOR, 0x30000800},

	MBDRC_FILTER_REG_DEFAULTS(0),
	MBDRC_FILTER_REG_DEFAULTS(1),
	MBDRC_FILTER_REG_DEFAULTS(2),
};

/* Default MBDRC parameters */
static const struct tegra210_mbdrc_config mbdrc_init_config = {
	.mode			= 0, /* Bypass */
	.rms_off		= 48,
	.peak_rms_mode		= 1, /* PEAK */
	.filter_structure	= 0, /* All-pass tree */
	.shift_ctrl		= 30,
	.frame_size		= 32,
	.channel_mask		= 0x3,
	.fa_factor		= 2048,
	.fr_factor		= 14747,

	.band_params[MBDRC_LOW_BAND] = {
		.band			= MBDRC_LOW_BAND,
		.iir_stages		= 5,
		.in_attack_tc		= 1044928780,
		.in_release_tc		= 138497695,
		.fast_attack_tc		= 2147483647,
		.in_threshold		= {130, 80, 20, 6},
		.out_threshold		= {155, 55, 13, 6},
		.ratio			= {40960, 8192, 2867, 2048, 410},
		.makeup_gain		= 4,
		.gain_init		= 419430,
		.gain_attack_tc		= 14268942,
		.gain_release_tc	= 1440547090,
		.fast_release_tc	= 2147480170,

		.biquad_params	= {
			/*
			 * Gains:
			 *
			 * b0, b1, a0,
			 * a1, a2,
			 */

			/* Band-0 */
			961046798, -2030431983, 1073741824,
			2030431983, -961046798,
			/* Band-1 */

Annotation

Implementation Notes