sound/soc/tegra/tegra210_peq.c

Source file repositories/reference/linux-study-clean/sound/soc/tegra/tegra210_peq.c

File Facts

System
Linux kernel
Corpus path
sound/soc/tegra/tegra210_peq.c
Extension
.c
Size
12584 bytes
Lines
436
Domain
Driver Families
Bucket
sound/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_peq.c - Tegra210 PEQ driver
//
// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include "tegra210_ope.h"
#include "tegra210_peq.h"

static const struct reg_default tegra210_peq_reg_defaults[] = {
	{ TEGRA210_PEQ_CFG, 0x00000013},
	{ TEGRA210_PEQ_CFG_RAM_CTRL, 0x00004000},
	{ TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL, 0x00004000},
};

static const u32 biquad_init_gains[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH] = {
	1495012349, /* Pre-gain */

	/* Gains : b0, b1, a0, a1, a2 */
	536870912, -1073741824, 536870912, 2143508246, -1069773768, /* Band-0 */
	134217728, -265414508, 131766272, 2140402222, -1071252997,  /* Band-1 */
	268435456, -233515765, -33935948, 1839817267, -773826124,   /* Band-2 */
	536870912, -672537913, 139851540, 1886437554, -824433167,   /* Band-3 */
	268435456, -114439279, 173723964, 205743566, 278809729,     /* Band-4 */
	1, 0, 0, 0, 0, /* Band-5 */
	1, 0, 0, 0, 0, /* Band-6 */
	1, 0, 0, 0, 0, /* Band-7 */
	1, 0, 0, 0, 0, /* Band-8 */
	1, 0, 0, 0, 0, /* Band-9 */
	1, 0, 0, 0, 0, /* Band-10 */
	1, 0, 0, 0, 0, /* Band-11 */

	963423114, /* Post-gain */
};

static const u32 biquad_init_shifts[TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH] = {
	23, /* Pre-shift */
	30, 30, 30, 30, 30, 0, 0, 0, 0, 0, 0, 0, /* Shift for bands */
	28, /* Post-shift */
};

static s32 biquad_coeff_buffer[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH];

static void tegra210_peq_read_ram(struct regmap *regmap, unsigned int reg_ctrl,
				  unsigned int reg_data, unsigned int ram_offset,
				  unsigned int *data, size_t size)
{
	unsigned int val;
	unsigned int i;

	val = ram_offset & TEGRA210_PEQ_RAM_CTRL_RAM_ADDR_MASK;
	val |= TEGRA210_PEQ_RAM_CTRL_ADDR_INIT_EN;
	val |= TEGRA210_PEQ_RAM_CTRL_SEQ_ACCESS_EN;
	val |= TEGRA210_PEQ_RAM_CTRL_RW_READ;

	regmap_write(regmap, reg_ctrl, val);

	/*
	 * Since all ahub non-io modules work under same ahub clock it is not
	 * necessary to check ahub read busy bit after every read.
	 */
	for (i = 0; i < size; i++)
		regmap_read(regmap, reg_data, &data[i]);
}

static void tegra210_peq_write_ram(struct regmap *regmap, unsigned int reg_ctrl,
				   unsigned int reg_data, unsigned int ram_offset,
				   unsigned int *data, size_t size)
{
	unsigned int val;
	unsigned int i;

	val = ram_offset & TEGRA210_PEQ_RAM_CTRL_RAM_ADDR_MASK;
	val |= TEGRA210_PEQ_RAM_CTRL_ADDR_INIT_EN;
	val |= TEGRA210_PEQ_RAM_CTRL_SEQ_ACCESS_EN;
	val |= TEGRA210_PEQ_RAM_CTRL_RW_WRITE;

Annotation

Implementation Notes