sound/soc/uniphier/aio-reg.h

Source file repositories/reference/linux-study-clean/sound/soc/uniphier/aio-reg.h

File Facts

System: Linux kernel
Corpus path: sound/soc/uniphier/aio-reg.h
Extension: .h
Size: 25289 bytes
Lines: 477
Domain: Driver Families
Bucket: sound/soc
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

linux/bitops.h

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef SND_UNIPHIER_AIO_REG_H__
#define SND_UNIPHIER_AIO_REG_H__

#include <linux/bitops.h>

/* soc-glue */
#define SG_AOUTEN                       0x1c04

/* SW view */
#define A2CHNMAPCTR0(n)                 (0x00000 + 0x40 * (n))
#define A2RBNMAPCTR0(n)                 (0x01000 + 0x40 * (n))
#define A2IPORTNMAPCTR0(n)              (0x02000 + 0x40 * (n))
#define A2IPORTNMAPCTR1(n)              (0x02004 + 0x40 * (n))
#define A2IIFNMAPCTR0(n)                (0x03000 + 0x40 * (n))
#define A2OPORTNMAPCTR0(n)              (0x04000 + 0x40 * (n))
#define A2OPORTNMAPCTR1(n)              (0x04004 + 0x40 * (n))
#define A2OPORTNMAPCTR2(n)              (0x04008 + 0x40 * (n))
#define A2OIFNMAPCTR0(n)                (0x05000 + 0x40 * (n))
#define A2ATNMAPCTR0(n)                 (0x06000 + 0x40 * (n))

#define MAPCTR0_EN                      0x80000000

/* CTL */
#define A2APLLCTR0                      0x07000
#define   A2APLLCTR0_APLLXPOW_MASK        GENMASK(3, 0)
#define   A2APLLCTR0_APLLXPOW_PWOFF       (0x0 << 0)
#define   A2APLLCTR0_APLLXPOW_PWON        (0xf << 0)
#define A2APLLCTR1                      0x07004
#define   A2APLLCTR1_APLLX_MASK           0x00010101
#define   A2APLLCTR1_APLLX_36MHZ          0x00000000
#define   A2APLLCTR1_APLLX_33MHZ          0x00000001
#define A2EXMCLKSEL0                    0x07030
#define   A2EXMCLKSEL0_EXMCLK_MASK        GENMASK(2, 0)
#define   A2EXMCLKSEL0_EXMCLK_OUTPUT      (0x0 << 0)
#define   A2EXMCLKSEL0_EXMCLK_INPUT       (0x7 << 0)
#define A2SSIFSW                        0x07050
#define A2CH22_2CTR                     0x07054
#define A2AIOINPUTSEL                   0x070e0
#define   A2AIOINPUTSEL_RXSEL_PCMI1_MASK      GENMASK(2, 0)
#define   A2AIOINPUTSEL_RXSEL_PCMI1_HDMIRX1   (0x2 << 0)
#define   A2AIOINPUTSEL_RXSEL_PCMI2_MASK      GENMASK(6, 4)
#define   A2AIOINPUTSEL_RXSEL_PCMI2_SIF       (0x7 << 4)
#define   A2AIOINPUTSEL_RXSEL_PCMI3_MASK      GENMASK(10, 8)
#define   A2AIOINPUTSEL_RXSEL_PCMI3_EVEA      (0x1 << 8)
#define   A2AIOINPUTSEL_RXSEL_IECI1_MASK      GENMASK(14, 12)
#define   A2AIOINPUTSEL_RXSEL_IECI1_HDMIRX1   (0x2 << 12)
#define   A2AIOINPUTSEL_RXSEL_MASK        (A2AIOINPUTSEL_RXSEL_PCMI1_MASK | \
					   A2AIOINPUTSEL_RXSEL_PCMI2_MASK | \
					   A2AIOINPUTSEL_RXSEL_PCMI3_MASK | \
					   A2AIOINPUTSEL_RXSEL_IECI1_HDMIRX1)

/* INTC */
#define INTCHIM(m)                       (0x9028 + 0x80 * (m))
#define INTRBIM(m)                       (0x9030 + 0x80 * (m))
#define INTCHID(m)                       (0xa028 + 0x80 * (m))
#define INTRBID(m)                       (0xa030 + 0x80 * (m))

/* AIN(PCMINN) */
#define IPORTMXCTR1(n)                   (0x22000 + 0x400 * (n))
#define   IPORTMXCTR1_LRSEL_MASK           GENMASK(11, 10)
#define   IPORTMXCTR1_LRSEL_RIGHT          (0x0 << 10)
#define   IPORTMXCTR1_LRSEL_LEFT           (0x1 << 10)
#define   IPORTMXCTR1_LRSEL_I2S            (0x2 << 10)
#define   IPORTMXCTR1_OUTBITSEL_MASK       (0x800003U << 8)
#define   IPORTMXCTR1_OUTBITSEL_32         (0x800000U << 8)
#define   IPORTMXCTR1_OUTBITSEL_24         (0x000000U << 8)
#define   IPORTMXCTR1_OUTBITSEL_20         (0x000001U << 8)
#define   IPORTMXCTR1_OUTBITSEL_16         (0x000002U << 8)
#define   IPORTMXCTR1_CHSEL_MASK           GENMASK(6, 4)
#define   IPORTMXCTR1_CHSEL_ALL            (0x0 << 4)
#define   IPORTMXCTR1_CHSEL_D0_D2          (0x1 << 4)
#define   IPORTMXCTR1_CHSEL_D0             (0x2 << 4)
#define   IPORTMXCTR1_CHSEL_D1             (0x3 << 4)
#define   IPORTMXCTR1_CHSEL_D2             (0x4 << 4)
#define   IPORTMXCTR1_CHSEL_DMIX           (0x5 << 4)
#define   IPORTMXCTR1_FSSEL_MASK           GENMASK(3, 0)
#define   IPORTMXCTR1_FSSEL_48             (0x0 << 0)
#define   IPORTMXCTR1_FSSEL_96             (0x1 << 0)
#define   IPORTMXCTR1_FSSEL_192            (0x2 << 0)
#define   IPORTMXCTR1_FSSEL_32             (0x3 << 0)
#define   IPORTMXCTR1_FSSEL_44_1           (0x4 << 0)
#define   IPORTMXCTR1_FSSEL_88_2           (0x5 << 0)
#define   IPORTMXCTR1_FSSEL_176_4          (0x6 << 0)
#define   IPORTMXCTR1_FSSEL_16             (0x8 << 0)
#define   IPORTMXCTR1_FSSEL_22_05          (0x9 << 0)
#define   IPORTMXCTR1_FSSEL_24             (0xa << 0)
#define   IPORTMXCTR1_FSSEL_8              (0xb << 0)
#define   IPORTMXCTR1_FSSEL_11_025         (0xc << 0)
#define   IPORTMXCTR1_FSSEL_12             (0xd << 0)
#define IPORTMXCTR2(n)                   (0x22004 + 0x400 * (n))

Annotation

Immediate include surface: `linux/bitops.h`.
Atlas domain: Driver Families / sound/soc.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.